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ATJ331X datasheet latest version: 1.0 2010-5-31 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 2 declaration circuit diagrams and other information relati ng to products of actions semiconductor company, ltd. (?actions?) are included as a means of illustrating typical applications. consequently, complete information sufficient for construction is not necessarily given. although the information has been examined and is believed to be accurate, actions makes no representations or warranties with respec t to the accuracy or completeness of the contents of this publication and disclaims any responsibility for inaccuracies. information in this document is provided solely to enable use of actions? products. the information presented in this document does not form part of any quotation or contract of sale. actions assumes no liability whatsoever, including infringe ment of any patent or copyright, for sale and use of actions? products, except as expre ssed in actions? terms and conditions of sale for. all sales of any actions products are co nditional on your agreement of the terms and conditions of recently dated version of acti ons? terms and conditions of sale agreement dated before the date of your order. this information does not convey to the purchaser of the desc ribed semiconductor devices any licenses under any patent rights, copyright, trademark rights, rights in trade secrets and/or know how, or any other intellectual property rights of actions or others, however denominated, whether by express or implied representation, by estoppel, or otherwise. information documented here relates solely to actions products described herein supersedes, as of the release date of this pu blication, all previously published data and specifications relating to such products pr ovided by actions or by any other person purporting to distribute such information. ac tions reserves the right to make changes to specifications and product desc riptions at any time without notice. contact your actions sales representative to obtain the latest spec ifications before placing your product order. actions product may contain design defects or errors known as anomalies or errata which may cause the products functions to deviate from published specifications. anomaly or ?errata? sheets relating to currently characte rized anomalies or errata are available upon request. designers must not rely on the abse nce or characteristics of any features or instructions of actions? products marked ?res erved? or ?undefined.? actions reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. actions? products are not designed, intended, authorized or warranted for use in any life support or other application where product failu re could cause or contribute to personal injury or severe property damage. any and all su ch uses without prior written approval of an free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 3 officer of actions and further testing and/or modification will be fully at the risk of the customer. copies of this document and/or other action s product literature, as well as the terms and conditions of sale agreement, may be obtained by visiting actions? website at http://www.actions-semi.com/ or from an authorized actions representative. the word ?actions?, the actions? logo, whether used separately and/or in combination, and the phase ?ATJ331X?, are trademarks of actions semiconductor company, ltd., names and brands of other companies and their products that may from time to time descriptively appear in this product data sheet are the tr ademarks of their respective holders; no affiliation, authorization, or endorsement by such persons is claimed or implied except as may be expressly stated therein. actions disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usage of trade. in no event shall actions be reliable for any direct, in cidental, indirect, special, punitive, or consequential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of actions or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether actions has been advised of the possibility of such damages or not. additional support additional product and company information can be obtained by visiting the actions website at: http://www.actions-semi.com free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 4 contents declarat ion.................................................................................................................... .. 2 contents ....................................................................................................................... ... 4 revision history ........................................................................................................... 10 1 introduc tion........................................................................................................... 11 1.1 over view................................................................................................................... ....... 11 1.2 features ................................................................................................................... ....... 11 2 pin descri ption ..................................................................................................... 13 2.1 atj3315.................................................................................................................... ....... 13 2.1.1 atj3315 pin assignment.......................................................................................... 13 2.1.2 atj3315 pin definition ............................................................................................. 14 3 ATJ331X block diagram ...................................................................................... 19 4 memory mapping ................................................................................................. 20 4.1 memory map ................................................................................................................. . 20 4.1.1 registers description................................................................................................ 21 5 system cont rol module ........................................................................................ 21 5.1 descri ption................................................................................................................ ...... 21 5.2 bus controller............................................................................................................. .... 22 5.2.1 mcuclk (mcu clock control register, 00h) ......................................................... 22 5.2.2 dma12cd (dma12 clock division register, 029h) ............................................. 23 5.2.3 cesel (chip enable selection register, 02h) ....................................................... 23 5.2.4 mcuctl (mcu-a15 control register, 04h) ............................................................ 24 5.2.5 graio (general random access io register, 03fh) ........................................... 25 5.2.6 module reset control register 2 ............................................................................ 25 5.3 dma channel 1 .............................................................................................................. 26 5.3.1 dma1saddr0 (dma1 source address 0 register, 06h).................................... 26 5.3.2 dma1saddr1 (dma1 source address 1 register, 07h) .................................... 27 5.3.3 dma1saddr3 (dma1 source address 3 register, 09h).................................... 27 5.3.4 dma1isa (dma1 ipm/idm/zram2 src address register, 0ah) ..................... 27 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 5 5.3.5 dma1daddr0 (dma1 destination address 0 register, 0bh) ........................... 28 5.3.6 dma1daddr1 (dma1 destination address 1 register, 0ch) ........................... 28 5.3.7 dma1daddr3 (dma1 destination address 3 register, 0eh)............................ 28 5.3.8 dma1ida (dma1 ipm/idm/zram2 dst address register, 0fh)...................... 29 5.3.9 dma1bcl (dma1 byte counter low, 10h) ............................................................ 29 5.3.10 dma1bch (dma1 byte counter high register, 011h) ........................................ 30 5.3.11 dma1m (dma1 mo de register, 012h)................................................................... 30 5.3.12 dma1com (dma1 co mmand register, 013h) ..................................................... 30 5.4 dma channel 2 .............................................................................................................. 31 5.4.1 dma2sa0 (dma2 source address 0 register, 014h).......................................... 31 5.4.2 dma2sa1 (dma2 source address 1 register, 015h).......................................... 32 5.4.3 dma2sa3 (dma2 source address 3 register, 017h).......................................... 32 5.4.4 dma2isa (dma2 ipm/idm/zram2 src address register, 018h)................... 32 5.4.5 dma2isa0 (dma2 destination address 0 register, 019h) ................................ 33 5.4.6 dma2isa1 (dma2 destination address 1 register, 01ah) ................................ 33 5.4.7 dma2isa3 (dma2 destination address 3 register, 01ch) ................................ 33 5.4.8 dma2ida (dma2 ipm/idm/zram2 dst address register, 01dh)................... 34 5.4.9 dma2bcl (dma2 byte count low register, 01eh)............................................... 34 5.4.10 dma2bch (dma2 byte count high register, 01fh) ............................................ 35 5.4.11 dma2m (dma2 mo de register, 020h)................................................................... 35 5.4.12 dma2com (dma2 co mmand register, 021h) ..................................................... 35 5.5 ctc ........................................................................................................................ ........... 36 5.5.1 ctcpres (ctc prescale register, 022h) ............................................................... 36 5.5.2 ctctpl (ctc t period low register, 023h) ........................................................... 37 5.5.3 ctctph (ctc t period high register, 024h).......................................................... 37 5.6 interrupt controller ....................................................................................................... . 38 5.6.1 dmacista (dma/ctc irq status register, 025h) ............................................... 38 5.6.2 mista (master interrupt status register, 026h)................................................... 39 5.6.3 mien (master interrupt enable register, 027h).................................................... 40 6 usb2.0 otg............................................................................................................ 41 6.1 descri ption................................................................................................................ ...... 41 6.2 feature .................................................................................................................... ........ 41 7 i2c inte rface ......................................................................................................... 42 7.1 description................................................................................................................ ...... 42 7.2 feature .................................................................................................................... ........ 42 7.3 register description ...................................................................................................... 42 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 6 7.3.1 i2caddr (i2c address register, 084h) ................................................................. 42 7.3.2 i2cctl (i2c control register, 085h)....................................................................... 43 7.3.3 i2csta (i2c status register, 086h) ........................................................................ 44 7.3.4 i2cdat (i2c data register, 087h)........................................................................... 45 8 spi interface ......................................................................................................... 45 8.1 descri ption................................................................................................................ ...... 45 8.2 feature .................................................................................................................... ........ 46 8.3 register description ...................................................................................................... 46 8.3.1 spictl (spi control register, a8h) ......................................................................... 46 8.3.2 spiirq (spi irq register, a9h) ............................................................................... 47 8.3.3 spista (spi status register, aah) .......................................................................... 48 8.3.4 spiclkdiv (spi clock divide control register, abh) ........................................... 48 8.3.5 spidat (spi data register, ach) ............................................................................. 49 8.3.6 spibcl (spi bytes count low register, adh)........................................................ 49 8.3.7 spibch (spi bytes count high register, aeh)....................................................... 49 9 uart inte rface...................................................................................................... 50 9.1 descri ption................................................................................................................ ...... 50 9.2 feature .................................................................................................................... ........ 50 9.3 register description ...................................................................................................... 50 9.3.1 baudrate (uart baud rate register, 079h) ...................................................... 51 9.3.2 uartctl (uart control register, 07ah)................................................................ 51 9.3.3 uartfdat (uart fifo data register, 07bh)........................................................ 52 9.3.4 uartms (uart mode & fifo status register, 07dh) ......................................... 53 9.3.5 uartrqs (uart drq/irq enable/status register, 07eh) ................................ 53 10 infrared remote co ntrol inte rface..................................................................... 55 10.1 introduction .............................................................................................................. ...... 55 10.2 features .................................................................................................................. ........ 55 10.3 register description ...................................................................................................... 55 10.3.1 ircctl (infrared remote control interface control register, 0x78)................. 55 10.3.2 ircsta (infrared remote control interface state register, 0x7f) ..................... 56 10.3.3 ircluc (infrared remote control low user code register, 0x3b) .................... 57 10.3.4 irchuc (infrared remote control high user code register, 0x3b)................... 57 10.3.5 irckdc (infrared remote cont rol key data code register, 0x3b).................... 58 10.3.6 ircakdc (infrared remote control anti key data code register, 0x3b)......... 58 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 7 11 spdif interface .................................................................................................... 59 11.1 description............................................................................................................... ....... 59 11.2 register description ...................................................................................................... 59 11.2.1 spdifctl (spdif control register, 080h) ............................................................. 59 11.2.2 spdifsta (spdif status register, 081h) .............................................................. 60 11.2.3 spdifdat (spdif fi fo data register, 082h) ....................................................... 60 11.2.4 spdif channel status register ............................................................................... 61 11.2.5 spdifch (spdif channel status register, 083h) ................................................ 61 12 clock manage ment unit...................................................................................... 62 12.1 description............................................................................................................... ....... 62 12.2 feature ................................................................................................................... ......... 62 12.3 register description ...................................................................................................... 62 12.3.1 rtc control register ................................................................................................. 62 12.3.2 hosc/pll ................................................................................................................ ... 68 12.3.3 clock selection unit .................................................................................................. 69 13 a/d d/a and head phone driver ......................................................................... 71 13.1 introduction .............................................................................................................. ...... 71 13.2 feature ................................................................................................................... ......... 71 13.3 adda analog diagram.................................................................................................. 71 13.4 dac....................................................................................................................... ............ 72 13.5 adc ....................................................................................................................... ........... 73 14 gpio/multi functi on.......................................................................................... 74 14.1 description............................................................................................................... ....... 74 14.2 feature ................................................................................................................... ......... 74 14.3 register description ...................................................................................................... 74 14.3.1 mfpsel (mfp select register, 0eeh)..................................................................... 75 14.3.2 gpioaouten (gpio_a output enable register, 0edh)........................................ 76 14.3.3 gpioainen (gpio_a inpu t enable register, 0efh) .............................................. 76 14.3.4 gpioadat (gpio_a data output/input register, 0f0h)...................................... 76 14.3.5 gpiobouten (gpio_b outp ut enable register, 0f1h)........................................ 77 14.3.6 gpiobinen (gpio_b inpu t enable register, 0f2h) .............................................. 77 14.3.7 gpiobdat (gpio_b data output/input register, 0f3h) ..................................... 77 14.3.8 gpiocouten (gpio_c outp ut enable register, 0f4h) ........................................ 78 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 8 14.3.9 gpiocinen (gpio_c inpu t enable register, 0f5h) .............................................. 78 14.3.10 gpiocdat (gpio_c data output/input register, 0f6h).................................. 79 14.3.11 gpiodouten (gpio_d outp ut enable register, 0f7h) ................................... 79 14.3.12 gpiodinen (gpio_d inpu t enable register, 0f8h).......................................... 79 14.3.13 gpioddat (gpio_d data output/input register, 0f9h)................................. 80 14.3.14 gpioeouten (gpi o_e [4:0] output enable register, 0fah) ........................... 80 14.3.15 gpioeinen (gpio_e [4:0] input enable register, 0fbh) ................................. 80 14.3.16 gpioedat (gpio_ e [4:0] data output/input register, 0fch) ........................ 81 14.3.17 gpiofouten (gpio_f [7:0] output enable register, 0fdh) ........................... 81 14.3.18 gpiofinen (gpio_f [7:0] input enable register, 0feh).................................. 81 14.3.19 gpiofdat (gpio_f [7:0] data output/input register, 0ffh) ......................... 82 14.3.20 gpioe0_vccoutsr (gpioe0_ vccout select register, 088h)...................... 82 15 pwm ...................................................................................................................... 83 15.1 introduction .............................................................................................................. ...... 83 15.2 feature ................................................................................................................... ......... 83 15.3 register description ...................................................................................................... 83 15.3.1 pwmctl (pwm control register, afh) .................................................................. 83 16 power manage ment unit..................................................................................... 85 16.1 introduction .............................................................................................................. ...... 85 16.2 function block diagram ............................................................................................... 85 16.3 dc-dc converters.......................................................................................................... . 87 16.3.1 dc-dc accurate and maximum output current.................................................... 87 16.3.2 dc-dc converter efficiency ...................................................................................... 88 16.4 linear regulators ......................................................................................................... . 88 16.4.1 regulators output voltage set ................................................................................ 88 16.4.2 regulators accurate and maximum output current............................................ 88 16.5 li-ion cell charger....................................................................................................... ... 89 16.6 a/d converters............................................................................................................ ... 90 16.7 programmable registers ............................................................................................. 91 16.7.1 system_ctl_rtcvdd, (system control register, 0a5h) (rtcvdd)................. 91 16.7.2 system_ctl_vdd (system set register, 0a6h)................................................. 92 16.7.3 voutctl (dc-dc & regulator output voltage control register, page0_089h) 93 16.7.4 lbnmi & adcirq (lbnmi & adci rq control register, page0_08ch) .............. 94 16.7.5 lradc1 (lradc1 data & fr equency register, page0_08dh)........................... 96 16.7.6 lradc2 (lradc2 input dete ct data register, page0_08eh) ........................... 96 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 9 16.7.7 batadc (battery voltage detect data register, page0_08fh).......................... 97 16.7.8 vccout control (vccout control register, page1_088h) ............................. 97 16.7.9 lradc3 (lradc3 data register, page1_089h) .................................................. 98 16.7.10 lradc4 (lradc4 data register, page1_08ah) .............................................. 98 16.7.11 lradc5 (lradc5 data register, page1_08bh) .............................................. 99 16.7.12 chg control (charger control register, page1_08ch) .................................... 99 16.7.13 chgdet (charge detect register, page1_08dh) ........................................... 101 16.7.14 chgasst (charger assist ant register, page1_08eh) ................................... 102 17 electrical char acteristics................................................................................... 104 17.1 absolute maximum ratings....................................................................................... 104 17.2 recommended power supply.................................................................................... 104 17.3 capacitance............................................................................................................... ... 105 17.4 dc characteristics ....................................................................................................... 105 17.5 ac characteristics........................................................................................................ 105 17.5.1 ac test input waveform ......................................................................................... 106 17.5.2 ac test output measuring points.......................................................................... 106 17.5.3 reset parameter...................................................................................................... 106 17.5.4 initialization parameter.......................................................................................... 106 17.5.5 gpio interface parameter...................................................................................... 107 17.5.6 ordinary rom parameter....................................................................................... 108 17.5.7 external system bus parameter ........................................................................... 109 17.5.8 bus operation........................................................................................................... 110 17.5.9 headphone driv er characteristics ........................................................................ 111 18 package dr awing ............................................................................................... 113 18.1 atj3315 package drawing ........................................................................................ 113 19 ordering in formation ......................................................................................... 114 19.1 recommended sold ering conditions....................................................................... 114 19.2 precaution against esd for semiconductors .......................................................... 114 19.3 handling of unused input pins for cmos ................................................................ 115 19.4 status before initialization of mos devices ............................................................ 115 20 appendix.............................................................................................................. 116 20.1 24.1 acronym and abbreviations.............................................................................. 116 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 10 revision history date revision description 2010-6-11 1.0 initial release; free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 11 1 introduction 1.1 overview ATJ331X is a third generation single-chip high ly integrated digital music system solution for devices dedicating to audio players etc. it includes an audio decoder with embedded ram and rom, adpcm record capabilities and usb interface for downloading music and uploading voice recordings. it also provides an interface to spdif, flash memory, led/lcd, button and switch inputs, headphones, micropho ne and fm radio input and control. the chip supports wma and other digital audio standards. for devices like usb-disk, it can act as a usb mass storage slave device to personal co mputer system. in addition, its low power consumption leads to long battery life and an efficient and flexible on-chip dc-dc converter allowing many different battery configurations , including 1xaa, 1xaaa and li-on. the built-in sigma-delta d/a includes a headphone driver to directly drive low impedance headphones. the a/d includes inputs for both microphone an d analog audio in to support voice recording and fm radio integration features. thus, it pr ovides a true ?all-in-one? solution that is ideally suited for highly optimized digital audio players. 1.2 features z support wma decoder, bit rate 32-384kbps, 8-48khz; z digital voice recording (adpcm); z on-chip multi-use ram ((22k+3*256)*8bit) and pcm ram (8k*8bit) that can be switched to be mcu memory space or dsp memory; z integrated mcu with dsu, the instru ction set is compatible with z80; z internal zram1 (( 16k-64 )*8),zram2((6k+256)*8) ,zram3(14k*8) accessed by mcu; z internal 17kx8 brom build in boot up and usb upgrade firmware; z internal sram access time<7ns, mrom access time<16ns; z external up to 4 (pcs) x 32m~4g bytes na nd type flash accessed by mcu or dma; z external smart media card; z support following memory card interface: multi media card specification version 4.2 (1/4/8 bit mode) secure digital card specificat ion version 2.0 (1/4-bit mode) memory stick version 1.43 (1/4-bit mode) free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 12 memory stick pro version 1.02 (1/4-bit mode) memory stick pro-hg version 1.01 (1/4/8-bit mode); z support 24mhz osc with on-chip pll for mcu and about 32khz rc oscillator; z 2-channel dma,1-channel ctc and interrupt controller for mcu; z energy saving with dynamic power management, supporting 1 cell, 2 cell and li-on; z support usb2.0 compliance phy+sie, rd/wr:6mb/5mb (nand flash base); z build in stereo 16-bit sigma-delta d/a; z enough gpios for all applications; z support i 2 c/spi/uart/ir/spdif interface; z support external 8080 series lcm driver interface; z support fm radio input and 40-level volume control; z support stereo 16-bit sigma-delta a/d for microphone/fm input, sample rate at 8/12/16/22/24/32/48khz; z mcu running at 48mhz (typ), f/w can progra m from dc up to 48mhz transparently; z d/a+pa snr: without a weight>91db; z a/d snr >90db, support difference/2-channle microphone; z headphone driver output 2x20mw @16ohm; z standby leakage current: <50ua (whole system); z low power consumption: <40mw@1.6v at typical audio decoder solution; z package at lqfp-64 (7x7mm) free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 13 2 pin description 2.1 atj3315 2.1.1 atj3315 pin assignment free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 14 2.1.2 atj3315 pin definition pin no. pin name i/o type driver reset default pu/pd/hold short description ce2- o h ext. memory chip enable 2 1 gpio_b1 bi 7ma / bit1 of general purpose i/o port b. ce1- o h ext. memory chip enable 1 2 gpio_b0 bi 7ma / bit0 of general purpose i/o port b 3 uvcc pwr / / power supply for usb 4 usbgnd pwr / / usb ground 5 usbdm a / h usb data minus 6 usbdp a / h usb data plus 7 aoutl ao / / int. pa left channel analog output 8 pavcc pwr / / power supply for power amplifier 9 aoutr ao / / int. pa right channel analog output 10 pagnd pwr / / power amplifier ground 11 vro_sense ai / / pa direct-drive virtual ground feedback 12 vro ao / / pa direct-drive virtual ground reference output 13 micin ai / / microphone pre-amplifier input 14 fminl ai / / left channel of fm line input 15 fminr ai / / right channel of fm line input 16 avcc pwr / / power supply of analog 17 agnd pwr / / analog ground 18 vrefi ai / / voltage reference input free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 15 19 lradc1 ai / / low resolution a/d input 1 20 vdd pwr / / digital core power 21 vcc pwr / / digital power pin 22 pwrmb ai / / power mode select 23 bat i / / pd200k battery voltage input. 24 dc5v ai / / 5.0v voltage 25 on_off ai system standby control 26 rtcvdd pwr rtc power supply 27 hosco ao / / high frequency crystal osc output 28 hosci ai / / high frequency crystal osc input 29 gnd pwr / / ground gpio_e0 bi z bit0 of general purpose i/o port e ms_bs o / pd50k ms card command interface 30 vccout pwr 10ma / 3.3v vccout 31 io_vcc pwr / / io for vcc dc-dc 32 lxvcc pwr / / vcc dc-dc pin 33 ngnd pwr / / nmos ground 34 lxvdd pwr / / vdd dc-dc pin 35 io_vdd pwr / z io for vdd dc-dc 36 vdd pwr / / digital core power ce5- o h ext. memory chip enable 5 gpio_a7 bi / bit7 of general purpose i/o port a 37 sirq- i 7ma / pd50k or pu50k system external interrupt request mrd- o h ext. memory read strobe 38 gpio_b2 bi 7ma / bit2 of general purpose i/o port b free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 16 mwr- o h ext. memory write strobe 39 gpio_b3 bi 7ma / bit3 of general purpose i/o port b rb1- i h pu2.5k nand type flash ready/busy status input. 40 gpio_b6 bi 7ma / bit6 of general purpose i/o port b gpio_c2 o z bit2 of general purpose i/o port c uart_rx i / uart rx i2s_lr o i2s lr 41 spdif_rx i 7ma / spdif rx gpio_e3 bi z bit3 of general purpose i/o port e mmc_clk1 o / clock1 for mmc/sd card 42 ms_clk o 10ma / pd50k clock for ms card gpio_c3 bi z bit3 of general purpose i/o port c uart_tx o / uart tx i2s_data o / i2s data 43 spdif_tx o 7ma / spdif tx gpio_e1 bi z bit1 of general purpose i/o port e mmc_cmd o / cmd of sd/mmc card interface 44 ms_bs o 10ma / pd50k bs of ms card interface ale o l address latch enable for nand flash 45 gpio_b4 bi 7ma / bit4 of general purpose i/o port b cle o l command latch enable for nand flash 46 gpio_b5 bi 7ma / bit5 of general purpose i/o port b 47 vcc pwr / / digital power pin free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 17 d7 bi l hold bit7 of ext. memory data bus 48 gpio_d7 bi 7ma / bit7 of general purpose i/o port d gpio_f3 bi z bit3 of general purpose i/o port f mmc_d3 bi / pu50k bit3 of mmc/sd card data bus 49 ms_d3 bi 10ma / pd50k bit3 of ms card data bus d6 bi l hold bit6 of ext. memory data bus 50 gpio_d6 bi 7ma / bit6 of general purpose i/o port d gpio_f2 bi z bit2 of general purpose i/o port f mmc_d2 bi / pu50k bit2 of mmc/sd card data bus 51 ms_d2 bi 10ma / pd50k bit2 of ms card data bus d5 bi l hold bit5 of ext. memory data bus 52 gpio_d5 bi 7ma / bit5 of general purpose i/o port d gpio_f1 bi z bit1 of general purpose i/o port f mmc_d1 bi / pu50k bit1 of mmc/sd card data bus 53 ms_d1 bi 10ma / pd50k bit1 of ms card data bus d4 bi l hold bit4 of ext. memory data bus 54 gpio_d4 bi 7ma / bit4 of general purpose i/o port d gpio_f0 bi z bit0 of general purpose i/o port f mmc_d0 bi / pu50k bit0 of mmc/sd card data bus 55 ms_d0 bi 10ma / pd50k bit0 of ms card data bus 56 d3 bi 7ma l hold bit3 of ext. memory data free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 18 bus gpio_d3 bi / bit3 of general purpose i/o port d d2 bi l hold bit2 of ext. memory data bus 57 gpio_d2 bi 7ma / bit2 of general purpose i/o port d 58 gnd pwr / / ground d1 bi l hold bit1 of ext. memory data bus 59 gpio_d1 bi 7ma / bit1 of general purpose i/o port d d0 bi l hold bit0 of ext. memory data bus 60 gpio_d0 bi 7ma / bit0 of general purpose i/o port d gpio_c7 bi z bit7 of general purpose i/o port c 61 spi_sclk o 7ma / clock of spi gpio_c6 bi z bit6 of general purpose i/o port c 62 spi_mosi bi 7ma / mosi of spi gpio_c5 bi z bit5 of general purpose i/o port c 63 spi_miso bi 7ma / miso of spi gpio_c4 bi z bit4 of general purpose i/o port c 64 spi_ss bi 7ma / ss of spi note: 1: pwr----power supply 2: ai-------analog input 3: ao------analog output 4: o--------output 5: i----------input 6: bi--------bidirection 7: uscu, uscl------uschimitcu, uschimitcl free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 19 8: pu--------pull up pd--------pull down 3 ATJ331X block diagram free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 20 4 memory mapping 4.1 memory map ATJ331X provides both on-chip rom and ram memories to aid in system performance and integration. zram1 16kb-64b 0000h 3fbfh 3fffh 16kb 7fffh 32kb ffffh dm1h 6.25kb dm1m 6.25kb dm1l 6.25kb pcmra mh 4kb pcmra ml 4kb dm2 4kb zram 2 (b1) 512b zram 2 (b2) 512b uram 2kb+192b zram3 9kb ce0 brom ce1 bank 32kb ce2 bank 32kb internal memory space (mcu.a15=0) entended memory space (mcu.a15=1) zram1 0000h~3fbfh ce1/ce2/ce3 8000h~ffffh dm1h/dm1m/dm1l 4000h~58ffh pcmramh/pcmraml 4000h~4fffh zram2(b1) 4000h~41ffh zram2(b2) 4200h~43ffh uram 7000h~78bfh zram3 4000h~63ffh dm2 4000h~4fffh free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 21 4.1.1 registers description 4.1.1.1 isramp (internal sram page register, 05h) bits description access reset 7 0: dm1 is mapped to dsp 1: dm1 is mapped to mcu/dma1/2/4/5 r/w 0 6 0: pcmramh is mapped to dsp 1: pcmramh is mapped to mcu/dma1/2/4/5 r/w 0 5 0: pcmraml is mapped to dsp 1: pcmraml is mapped to mcu/dma1/2/4/5 r/w 0 4 0: dm2 is mapped to dsp 1: dm2 is mapped to mcu/dma1/2/4/5 r/w 0 3 reserved / / 2:0 extended sram page address bit. 0 0 0: dm1 low byte 0 0 1: dm1 middle byte 0 1 0: dm1 high byte 0 1 1: zram3+ uram 1 0 0: pcmram low byte 1 0 1: pcmram high byte 1 1 0: dm2 1 1 1: zram2 (b1+b2) r/w 0 5 system control module 5.1 description this chapter describes the extended 8 bit mcu with ram access, its bus controller, direct memory access (dma) controller, ctc module and interrupt controller. free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 22 5.2 bus controller 5.2.1 mcuclk (mcu clock control register, 00h) bits description access reset 7:6 number of wait states fo r external memory access 0 0: 0, zero wait state(default) 0 1: 1, one wait state 1 0: 2, two wait states 1 1: 3, three wait states if access internal brom no wait state needed. r/w 0 5:4 mcu clock source select 0 0: losc 0 1: hosc 1 0: reserved 1 1: mcu pll the time needed for mcu clock source switch: 1 from losc to mcupl, it has to wait for (pll_freq/losc) +1 cycle, for example losc=32768khz, mcupll=60mhz, then, it has to wait for (60/0.032768)+1=1833 clocks. 2 from losc to hosc, it has to wait: hosc/ losc clock; from high frequency or pll switch to losc, it has to wait for 1 clock. r/w 0 3 reserved / / 2:0 mcu clock division control 0 0 0 /01 (default) 0 0 1 /02 0 1 0 /04 0 1 1 /08 1 0 0 /16 1 0 1 /32 1 1 0 /64 1 1 1 /dc r/w 0 it may take a while before mcu clock change . when the mcu clock is stopped (dc), there are several ways to recover the clock to non-divided losc clock source: 1. push reset button free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 23 2. power on reset 3. alarm irq 4. sirq 5. usb wake up irq 6. lradc1 irq 5.2.2 dma12cd (dma12 clock division register, 029h) bits description access reset 7 software reset. writing 1 to this bit will reset system, after finishing it will be cleared. its operation is equal to external reset- pin. r/w 0 6 software reset flag. 0: software reset not occurred, 1: software reset occurred. writing 1 to this bit will clear it. r/w 0 5:3 reserved. / / 2:0 dma1/dma2 clock division control 0 0 0 /01 0 0 1 /02 0 1 0 /04 0 1 1 /08 1 0 0 /16 1 0 1 /32 1 1 0 /64 1 1 1 /128 r/w 000 5.2.3 cesel (chip enable selection register, 02h) bits description access reset 7 multiplexing of gpioa7 and ce5- 0: gpioa7 1: ce5- when sirq enabled, ce5- and gpio is shielded for sirq r/w 1 6 multiplexing of gpioa6 and ce4- 0: gpioa6 1: ce4- r/w 1 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 24 5 multiplexing of gpioa5 and ce3- 0: gpioa5 1: ce3- r/w 1 4 multiplexing of gpiob1 and ce2- 0: gpiob1 1: ce2- r/w 1 3 multiplexing of gpiob0 and ce1- 0: gpiob0 1: ce1- r/w 1 2:0 chip enable selection: 000b, decode to ce0- 001b, decode to ce1- 010b, decode to ce2- 011b, decode to ce3- 100b, decode to ce4- 101b, decode to ce5- 110b, decode to ce6-(no pin) 111b, decode to ce7-(no pin) r/w 000 5.2.4 mcuctl (mcu-a15 control register, 04h) bits description access reset 7 watch dog flag, 1 means wd reset or irq ever occurred. writing 1 to this bit to clear it. r/w 0 6 external reset flag, 1 means external reset had been asserted, writing 1 to this bit to clear it. r/w 0 5 low bat nmi- pending. the lbnmi- voltage can be set by the lb register. if lbnmi- occurred, this bit will be set. writing 1 to this bit will clear it. r/w 0 4 reserved / / free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 25 3 sirq trigger edge select: 0: negative edge 1:positive edge when sirq is enabled and this bit is set 0, the 200k pull high register will be enabled. when sirq is enabled and this bit is set 1 the 200k pull low register will be enabled. r/w 0 2 sirq- enable. 0: disable 1: enable. sirq will be enabled by this bi t, and it can be trigged by the signal connected to sirq- pin on the negative or positive edge selected by bit3 of this register r/w 0 1 lbnmi- enable. 0: disable 1: enable. r/w 0 0 a15 control bit. 0: force mcu?s a15 to be 1, execute program from ce0 memory space. 1: for normal operation, the boot code after power on reset must be jp 800xh followed by an io write to 04h to set this bit for normal operation. r/w 0 5.2.5 graio (general random access io register, 03fh) bits description access reset 7:0 this register is a general random access io and can be written and read by mcu/dma1/dma2/dma4/dma5 r/w 0 5.2.6 module reset control register 2 mrcr2 (module reset control register 2, 3dh) bits description access reset 7 ram & rom bist reset 0 reset 1 normal r/w 1 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 26 6 on_off press status 1: when the on_off key is pressed down, the on_off pin?s voltage goes 0v the press status bit will be set to one. 0: when the on_off is up, the on_off pin?s voltage go above 0.8v and then the press status bit will be cleared to zero. r/w 0 5 adc reset 0 reset 1 normal r/w 1 4 dac reset 0 reset 1 normal r/w 1 3 usb reset 0 normal 1 reset (usb module is defaulted as reset status, but the register?s default remains unchanged and is 1.) r/w 1 2 dma4 reset 0 reset 1 normal r/w 1 1 irc gpio mapping select 0 mapping to gpio f5 1 mapping to gpio c2 r/w 1 0 dma1 & dm2 reset 0 reset 1 normal r/w 1 5.3 dma channel 1 5.3.1 dma1saddr0 (dma1 source address 0 register, 06h) bits description access reset 7:0 dma1sa[7:0] r/w x free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 27 5.3.2 dma1saddr1 (dma1 source address 1 register, 07h) bits description access reset 7:0 dma1sa[15:8] r/w x 5.3.3 dma1saddr3 (dma1 source address 3 register, 09h) bits description access reset 7 external memory select, 0: internal memory, 1: external memory r/w 0 6 int. memory select, 0:zram1, 1: dm1/pcmram/dm2/zram2 (b1, b2, uram)/ zram3 r/w 0 5:3 reserved / / 2:0 dma1sa[25:23] r/w x 5.3.4 dma1isa (dma1 ipm/idm/zram 2 src address register, 0ah) bits description access reset 7:3 reserved / / 2:0 extended sram page address bit. 0 0 0: dm1 low byte 0 0 1: dm1 middle byte 0 1 0: dm1 high byte 0 1 1: zram3+uram 1 0 0: pcmram low byte 1 0 1: pcmram high byte 1 1 0: dm2 1 1 1: zram2 (b1+b2) b1: 4000h-41ffh b2: 4200h-43ffh uram: 7000h-78bfh r/w xxx free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 28 5.3.5 dma1daddr0 (dma1 destination address 0 register, 0bh) bits description access reset 7:0 dma1da[7:0] r/w xxh 5.3.6 dma1daddr1 (dma1 destination address 1 register, 0ch) bits description access reset 7:0 dma1da[15:8] r/w xxh 5.3.7 dma1daddr3 (dma1 destination address 3 register, 0eh) bits description access reset 7 external memory select, 0: int. memory, 1: external memory r/w 0 6 int. memory select, 0: zram1, 1: dm1/pcmram/dm2/zram2 (b1, b2, uram) /zram3 r/w 0 5:3 reserved / / free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 29 2:0 dmada[25:23] cex select bit 000: ce0- selected 001: ce1- selected 010: ce2- selected 011: ce3- selected 100: ce4- selected 101: ce5- selected 110: ce6- selected 111: ce7- selected r/w x 5.3.8 dma1ida (dma1 ipm/idm/zram2 dst address register, 0fh) bits description access reset 7:3 reserved / / 2:0 extended sram page address bit. 0 0 0: dm1 low byte 0 0 1: dm1 middle byte 0 1 0: dm1 high byte 0 1 1: zram3+uram 1 0 0: pcmram low byte 1 0 1: pcmram high byte 1 1 0: dm2 1 1 1: zram2(b1+b2) b1: 4000h-41ffh b2: 4200h-43ffh uram: 7000h-78bfh r/w 000 5.3.9 dma1bcl (dma1 byte counter low, 10h) bits description access reset 7:0 dma1bc[7:0] r/w xx free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 30 5.3.10 dma1bch (dma1 byte counter high register, 011h) bits description access reset 7 reserved / / 6:0 dma1bc[14:8], maximum transferred byte is 32kbytes r/w xx 5.3.11 dma1m (dma1 mode register, 012h) bits description access reset 7:6 dma1 wait state select 0 0 0 wait state 0 1 1 wait state 1 0 2 wait states 1 1 3 wait states r/w 0 5 reserved / / 4 dma1 dst down count, 0: up count, 1: down count r/w 0 3 dma1 src down count, 0: up count, 1: down count r/w 0 2 reserved / / 1 dma1 dst is io. 0: memory 1: io r/w 0 0 dma1 src is io. 0: memory 1: io r/w 0 5.3.12 dma1com (dma1 command register, 013h) bits description access reset 7 dma1 tc irq enable. 0: disable irq. 1: enable irq when dma1 finishes the whole block transfer. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 31 6 dma1 half transfer irq enable. 0: disable irq. 1: enable irq when dma1 finishes half of the block transfer. r/w 0 5 dma1 continue block transfer enable. 0: disable continuous block transfer mode and bit 1 of this register will be cleared when the last byte of the block is transferred. 1: enables continuous block transfer mode and bit 1 of this register will not be cl eared and src address counter/dst address counter/byte length counte r will be reloaded with their corresponding registers when dma1 finishes the block transfer. r/w 0 4 dma1 priority 0: dma1 low priority 1: dma1 high priority. when both dma1 priority and dma2 priority are set or cleared simultaneously, the priority is in first start-first-finish style. r/w 0 3:2 external trigger 0 0 drq1a, uart/ir tx drq 0 1 drq1b, dsp codec input drq 1 0 drq1c, spi tx drq 1 1 drq1d, spdif tx drq r/w 0 1 external drq trigger enable, 0: disable external drq trigger, 1: enable. r/w 0 0 dma1 start. after tc the bit will be cleared. the low-go-high edge of this bit will load src start address, dst start address, byte count into the current working counters. r/w 0 5.4 dma channel 2 5.4.1 dma2sa0 (dma2 source address 0 register, 014h) bits description access reset 7:0 dma2sa[7:0] r/w xx free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 32 5.4.2 dma2sa1 (dma2 source address 1 register, 015h) bits description access reset 7:0 dma2sa[15:8] r/w xx 5.4.3 dma2sa3 (dma2 source address 3 register, 017h) bits description access reset 7 external memory select, 0: internal memory,1: external memory r/w 0 6 internal memory select 0:zram1, 1: dm1/pcmram/dm2/zram2 (b1, b2, uram) /zram3 r/w 0 5:3 reserved / / 2:0 dma2sa[25:23] cex select bit 000: ce0- selected 001: ce1- selected 010: ce2- selected 011: ce3- selected 100: ce4- selected 101: ce5- selected 110: ce6- selected 111: ce7- selected r/w x 5.4.4 dma2isa (dma2 ipm/idm/zram 2 src address register, 018h) bits description access reset 7:3 reserved / / free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 33 2:0 extended sram page address bit. 0 0 0: dm1 low byte 0 0 1: dm1 middle byte 0 1 0: dm1 high byte 0 1 1: zram3+uram 1 0 0: pcmram low byte 1 0 1: pcmram high byte 1 1 0: dm2 1 1 1: zram2 (b1+b2) b1: 4000h-41ffh b2: 4200h-43ffh uram: 7000h-78bfh r/w xxx 5.4.5 dma2isa0 (dma2 destination address 0 register, 019h) bits description access reset 7:0 dma2da[7:0] r/w xx 5.4.6 dma2isa1 (dma2 destination address 1 register, 01ah) bits description access reset 7:0 dma2da[15:8] r/w xx 5.4.7 dma2isa3 (dma2 destination address 3 register, 01ch) bits description access reset 7 external memory select, 0: internal memory, 1: external memory r/w 0 6 internal memory select 0: zram1, 1: dm1/pcmram/dm2/zram2 (b1, b2, uram) /zram3 r/w 0 5:3 reserved / / free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 34 2:0 dma2da[25:23] cex select bit 000: ce0- selected 001: ce1- selected 010: ce2- selected 011: ce3- selected 100: ce4- selected 101: ce5- selected 110: ce6- selected 111: ce7- selected r/w x 5.4.8 dma2ida (dma2 ipm/idm/zram2 dst address register, 01dh) bits description access reset 7:3 reserved / / 2:0 extended sram page address bit. 0 0 0: dm1 low byte 0 0 1: dm1 middle byte 0 1 0: dm1 high byte 0 1 1: zram3+uram 1 0 0: pcmram low byte 1 0 1: pcmram high byte 1 1 0: dm2 1 1 1: zram2 (b1+b2) b1: 4000h-41ffh b2: 4200h-43ffh uram: 7000h-78bfh r/w xxx 5.4.9 dma2bcl (dma2 byte count low register, 01eh) bits description access reset 7:0 dma2bc[7:0] r/w xx free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 35 5.4.10 dma2bch (dma2 byte count high register, 01fh) bits description access reset 7 reserved / / 6:0 dma2bc[14:8] r/w xx 5.4.11 dma2m (dma2 mode register, 020h) bits 5.4.11.1 description access reset 7:6 dma2 wait state select 0 0 0 wait state 0 1 1 wait state 1 0 2 wait states 1 1 3 wait states r/w 0 5 reserved / / 4 dma2 dst down count. 0: up count, 1: down count. r/w 0 3 dma2 src down count. 0: up count, 1: down count. r/w 0 2 reserved / / 1 dma2 dst is io. 0: memory, 1: io. r/w 0 0 dma2 src is io. 0: memory, 1: io. r/w 0 5.4.12 dma2com (dma2 command register, 021h) bits description access reset 7 dma2 tc irq enable. 0: disable irq. 1: enable irq when dma2 finishes whole block transfer. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 36 6 dma2 half transfer irq enable. 0: disable irq. 1: enable irq when dma2 finishes half of the block transfer. r/w 0 5 dma2 continue block transfer enable. 0: disables continuous block transfer mode and bit 1 of this register will be cleared when the last byte of the block is transferred. 1 enables continuous block transfer mode and bit 1 of this register will not be cl eared and src address counter/dst address counter/byte length counte r will be reloaded with their corresponding registers when dma2 finishes the block transfer. r/w 0 4 dma2 priority, 0: dma2 low priority, 1: dma2 high priority when both dma1 priority and dma2 priority are se t or cleared simultaneously, the priority is in first start first finished style. r/w 0 3:2 external drq trigger select 0 0 drq2a, uart/ir rx drq 0 1 drq1b, dsp input drq 1 0 drq2c, spi rx drq 1 1 drq2d, spdif rx drq r/w 0 1 external drq trigger enable, 0: disable external drq trigger, 1: enable. r/w 0 0 dma2 start. after tc the bit will be cleared. the low-go-high edge of this bit will load src start address, dst start address, byte count into the current working counters. r/w 0 5.5 ctc 5.5.1 ctcpres (ctc prescale register, 022h) bits description access reset 7 ctc1 enable 0: disable, 1: enable. r/w 0 6 ctc2 enable 0: disable, 1: enable. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 37 5 ctc1 irq pending bit writing 1 to this bit will clear it. r/w 0 4 ctc2 irq pending bit writing 1 to this bit will clear it. 3:0 pre-scale register. 0000: ctc1/ctc2 clock is /1 of the hosc. 0001: /2 0010: /4 0011: /8 0100: /16 0101: /32 0110: /64 0111: /128 1000: /256 1001: /512 others are reserved r/w 0 note: ctc1 is a non-maskable interrupt for z80, but ctc2 is a maskable interrupt for z80. please refer to register 25h bit7. 5.5.2 ctctpl (ctc t period low register, 023h) when 25h.bit7 = 0 ctctpl (ctc1 t period low register, 023h) bits description access reset 7:0 tperiod[7:0], period low byte register of ctc rw xx when 25h.bit7 = 1 ctctpl(ctc2 t period low register, 023h) bits description access reset 7:0 tperiod[7:0], period low byte register of ctc rw xx 5.5.3 ctctph (ctc t period high register, 024h) when 25h.bit7 = 0 ctctph (ctc1 t period high register, 024h) free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 38 bits description access reset 7:0 tperiod[15:8], period register of ctc rw xx when 25h.bit7 = 1 ctctph (ctc2 t period high register, 024h) bits description access reset 7:0 tperiod[15:8], period register of ctc rw xx note: the two t period registers are both for ctc1 and ctc2, using a bit to select page. the bit is 25h.bit7. when 25h.bit7 is ?0?, the two registers are for ctc1. otherwise, they are for ctc2. 5.6 interrupt controller note: all interrupt pending bits will not be influeneced by enable bit. 5.6.1 dmacista (dma/ctc irq status register, 025h) bits description access reset 7 ctc1/2 t period register select. 0: t period resisters are for ctc1 1: t period resisters are for ctc2 rw 0 6 dma2 half transfer irq pending, writing 1 to this bit will clear it. r/w 0 5 dma2 end transfer irq pending, writing 1 to this bit will clear it. r/w 0 4 dma1 half transfer irq pending, writing 1 to this bit will clear it. r/w 0 3 dma1 end transfer irq pending, writing 1 to this bit will clear it. r/w 0 2 sirq- pending, writing 1 to this bit will clear it. r/w 0 1 reserved. / / 0 software controlled dma1/dma2 reset signal, the low-go-high edge of this bit will generate a pulse to reset dma1/dma2 state machine, bytes counter, and clear h.w drq, etc status. after the pulse the bit will be cleared to 0. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 39 5.6.2 mista (master interrupt status register, 026h) bits description access reset 7 a/d interrupt(3) 1. wire-control irq 2. audio adc irq 3. charge status irq this bit will be automatically cleared only when all the a/d int pending bits are cleared, otherwise it is unchanged. r/w 0 6 reserved / / 5 rtc interrupt.(4) 1. watch dog irq 2. rtc timer irq 3. rtc alarm irq 4. 2hz rtc irq this bit will be automatically cleared only when all the rtc int pending bits are cleared, otherwise it is unchanged. r/w 0 4 dma1/2/4/sd/mmc/ms/ctc interrupt (6) 1. dma1 tc/half transfer irq 2. dma2 tc/half transfer irq 3. dma4 irq 4. sd/mmc transfer end irq fifo irq or sdio irq 5. ms transfer finished irq 6. ctc irq this bit will be automatically cleared only when all the dma1/2/4/sd/mmc/ms/ctc int pending bits are cleared, otherwise it is unchanged. r/w 0 3 sirq/i2c/spi/rb interrupt(4) 1. external irq (sirq) 2. i2c irq 3. spi rx/tx irq 4. rb1/rb2 rdy irq or state machine ending irq this bit will be automatically cleared only when all the sirq/i2c/spi/rb int pending bits are cleared, otherwise it is unchanged. r/w 0 2 reserved r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 40 1 uart/ir/spdif/irc interrupt(2) 1. uart/ir rx irq 2. spdif block in irq or data in irq 3. irc rx irq this bit will be automatically cleared only when all the uart/ir/spdif/irc int pending bits are cleared, otherwise it is unchanged. r/w 0 0 dsp interrupt (4) pending, this bit will be automatically cleared only when all the dsp int pending bit is cleared, otherwise unchanged. r/w 0 5.6.3 mien (master interrupt enable register, 027h) bits description access reset 7 a/d interrupt enable, 0: disable, 1: enable. r/w 0 6 reserved / / 5 rtc interrupt enable, 0: disable, 1: enable. r/w 0 4 dma1/2/4/sd/mmc/ms/ctc interrupt enable. 0: disable. 1: enable r/w 0 3 sirq/i2c/spi/rb interrupt enable. 0: disable, 1: enable. r/w 0 2 usb interrupt enable, 0: disable, 1: enable. r/w 0 1 uart/ir/spdif/irc interrupt enab le, 0: disable, 1: enable. r/w 0 0 dsp interrupt enable, 0: disable, 1: enable. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 41 6 usb2.0 otg 6.1 description actions usb2.0 otg (aotg) is a dual-role- device (drd) controller which complies with on-the-go supplement to the usb2.0 specification v1.0a. 6.2 feature z complies with on-the-go supplement to th e usb2.0 specification revision 1.0a; z utmi+ level2 transceiver macrocell interface; z supports session request protocol (srp) and host negotiation protocol (hnp); z supports point-to-point communication with one low-speed, full-speed or high-speed device in host mode (no hub support); z supports full-speed or high-speed in peripheral mode; z supports 2 in endpoint and 1 ou t endpoint except endpoint0; z supports bulk isochronous and interrupt transfer; z partially configurable endpoint buffer size, endpoint type and single, double triple or quad buffering; z integrated synchronous ram as endpoint fifos; z supports suspend, resume and power managements function; z support remote wakeup; z support udisk mode high speed dma panel; free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 42 7 i2c interface 7.1 description i2c can be configured as either a master or slave device. in master mode it generates the clock (i2c_scl) and initiates transactions on the data line (i2c_s da). data on the i2c bus is byte oriented. multi-master mode, 10-bit address and hi-speed mode are not supported. 7.2 feature z two-wire serial interface. z 100khz and 400khz compatibility 7.3 register description i2c module registers address name description 84h i2caddr i2c address register 85h i2cctl i2c control register 86h i2csta i2c status register 87h i2cdat i2c data register 7.3.1 i2caddr (i2c address register, 084h) this register is for setting i2c slav e address in master or slave mode. bits description access reset 7:1 i2c slave address. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 43 0 in master mode, r/w control bit in slave mode: i2c slave address match. 0: match, send irq to mcu; 1: not match, do not send irq in master mode, address 7-bit is used to setting the slave address, so the i2c data regi ster just store the data. in slave mode, address 7-bit is used to compare with the address that master sending out. so the i2c data register can store the address and data. r/w 0 7.3.2 i2cctl (i2c control register, 085h) this register is for enabling i2c and i2c irq, selecting i2c operating mode, ack generation. bits description access reset 7 i2c enable. 0: disable 1: enable i2c receive and transmit channel. r/w 0 6 in master mode, operating mode select. 0: standard (100kbps) 1: fast (400kbps) in slave mode, start irq enable. 0: disable 1: enable r/w 0 5 i2c irq enable, 0:disable, 1:enable r/w 0 4 i2c master or slave select. 0:master, 1:slave r/w 0 3:2 i2c cond [1..0]. generates a bus control. (master mode only) 0 0 no effect 0 1 generate start condition 1 0 generate stop condition 1 1 scl will be released to high level to generate the repeated start condition r/w 0 1 writing 1 to this bit will release the clock and data line to idle. r/w 0 0 in transmitting ack ----ack enable. controls generation of an ack signal in receiving mode 1: do not generate an ack at 9 th scl , 0: generate an ack signal at 9 th scl. in receiving ack ---- last received bit. use the read only bit to check the ack signals from the receiver (slave), or to monitor sda operation of sda when writing 11 to control reg bit[3..2] for repeated starts. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 44 7.3.3 i2csta (i2c status register, 086h) this register is for displaying current i2c status. bits description access reset 7 i2c buffer flag. automatically cleared when i2c data reg is written or read automatically set and the buffer is empty in transmit mode or the buffer is full in receiving mode. writing 1 to this bit will clear it. transmit 0: transmit in progress 1: transmit complete receive 0: receive in progress 1: receive complete r/w 0 6 i2c stop bit. this bit is cleare d when the i2c mode is disabled or when the start bit was detected at last. writing 1 to this bit will clear it. 1: indicate that the stop bit was detected at last 0: stop bit was not detected at last r/w 0 5 i2c start bit. this bit is cleare d when the i2c mode is disabled or when the stop bit was detected at last. writing 1 to this bit will clear it. 1: indicate that the start bit was detected at last 0: start bit was not detected at last r/w 0 4 i2c r/w bit. read/write bit information. this bit holds the r/w bit information following the last address match. this bit is valid only from the address match to the next start bit, stop bit or nak bit. 1: read 0: write r/w 0 3 i2c d/a. data/address bit 1: indicate the last byte received or transmitted was data. 0: indicate the last byte received or transmitted was address. r/w 0 2 i2c irq pending bit. writing 1 to this bit will clear it. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 45 1 i2c overflow bit. writing 1 to this bit will clear it. 1: a new byte is received while the previous byte has not been read 0: no overflow r/w 0 0 reserved / / note: whenever overflow is set, nak will occur automatically. 7.3.4 i2cdat (i2c data register, 087h) this register is for writing data to or reading data from i2c data register. bits description access reset 7:0 i2c data/address[7:0] r/w 00 8 spi interface 8.1 description ATJ331X spi can be configured as either a master or a slave device. during a spi transfer, data is shifted out and shifted in (transmitted and received) simultaneously. the spi_sck line synchronizes the shifting and samplin g of the information. it is an output when the spi is configured as a master or an inpu t when the spi is configured as a slave. spi uses a couple of parameters called cloc k polarity (cpol) and clock phase (cpha) to determine when data is valid wi th respect to the clock signal . cpol determines whether the leading edge is defined to be the rising or falling edge of the clock (and vice versa for the trailing edge). cpha determines whether the lead ing edge is used for setup or sample (and vice versa for the trailing edge). the foll owing table summarizes the various settings. cpol/cpha leading edge trailing edge spi mode 0/0 sample, rising setup, falling 0 0/1 setup, rising sample, falling 1 1/0 sample, falling setup, rising 2 1/1 setup, falling sample, rising 3 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 46 8.2 feature ? master and slave modes of operation. ? dma interface supporting data transfer from bulk memory to the synchronous serial interface ? support spi full-duplex mode and half-duplex mode. ? master and slave mode boot options to down load the code image from the spi norflash. 8.3 register description spi module registers address name description a8h spictl spi control register a9h spiirq spi irq register aah spista spi status register abh spiclkdiv spi clock divide control register ach spidat spi data register adh spibcl spi byte count low register aeh spibch spi byte count high register 8.3.1 spictl (spi control register, a8h) this register is used for enabling spi module, selecting spi mode and spi ss output voltage. bits description access reset 7 spi enable 0: disable; 1: enable spi receiving and transmiting channel r/w 0 6 spi master/slave select 0: master 1: slave r/w 0 5 lsb/msb first select 0: transmit and receive msb first 1: transmit and receive lsb first r/w 0 4 spi ss pin control output, this bit is valid only in master mode 1: output high 0: output low r/w 1 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 47 3:2 spi mode select cpol cpha 00: mode 0 01: mode 1 10: mode 2 11: mode 3 r/w 11 1 two wire mode enable bit 0: normal 4 wire mode 1: two wire mode, use two pins only, spi_clk and spi_mosi r/w 00 0 spi full-duplex or half-duplex mode select 0: full-duplex mode 1: half-duplex mode r/w 0 8.3.2 spiirq (spi irq register, a9h) this register is for enabling spi drq/irq and selecting spi drq/irq trigger threshold. bits description access reset 7 spi tx drq enable 0: disable 1: enable r/w 0 6 spi rx drq enable 0: disable 1: enable r/w 0 5 spi tx irq/drq trigger threshold control. 0: trigger spi tx irq/drq when spi tx fifo is half empty 1: trigger spi tx irq/drq when spi tx fifo is empty r/w 0 4 spi rx irq/drq trigger threshold control. 0: trigger spi rx irq/drq when spi rx fifo is half full 1: trigger spi rx irq/drq when spi rx fifo is not empty r/w 0 3 spi tx irq pending , 0: no tx irq pending 1: tx irq pending. writing 1 to this bit will clear it. r/w 0 2 spi rx irq pending 0: no rx irq pending 1: rx irq pending. writing 1 to this bit will clear it. r/w 0 1 spi tx irq enable 0: disable, 1: enable r/w 0 0 spi rx irq enable 0: disable, 1: enable r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 48 8.3.3 spista (spi status register, aah) this register is used for displaying current spi fifo status. bits description access reset 7 spi tx fifo empty 0: not empty 1: empty r 1 6 spi tx fifo full 0: not full 1: full r 0 5 spi rx fifo empty 0: not empty 1: empty r 1 4 spi rx fifo full 0: not full 1: full r 0 3 spi tx fifo error pending . writing 1 to this bit will clear it and reset the tx fifo, otherwise it is unchanged. r/w 0 2 spi rx fifo error pending . writing 1 to this bit will clear it and reset the tx fifo, otherwise it is unchanged. r/w 0 1 spi transfer complete this bit is set to 1 at the end of an spi transfer, and cleared by the read or write to the spi data register. r/w 0 0 reserved / / 8.3.4 spiclkdiv (spi clock divide control register, abh) this register is used for setting spi source cl ock divide factor, and selecting spi read mode. bits description access reset 7 spi read clock delay enable bit (v alid only in half-duplex mode) 0: disable clock delay 1: enable clock delay r/w 0 6:0 spi clock divide factor (spiclkfactor) [6:0] if spi clock divide factor is 0, spi clk = mcu pll, other spi clk = (mcu pll) / (spiclkfactor[6:0]*2) r/w 1111111 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 49 8.3.5 spidat (spi data register, ach) this register is used for writing data to spi tx fifo or reading data from spi rx fifo. bits description access reset 7:0 spi data[7:0] writing this field will send 1 byte to 8bitx8 levels depth spi fifo. reading this field will fetch 1 byte from 8bitx8 levels depth spi fifo. r/w x 8.3.6 spibcl (spi bytes count low register, adh) this register is used for setting spi bytes counter low bits in the spi norflash mode. bits description access reset 7:0 bytes counter low bits [7: 0] r/w 0 8.3.7 spibch (spi bytes count high register, aeh) this register is used for setting spi bytes coun ter high bits, selecting spi data i/o mode and high read rate mode delay time in the spi norflash mode. bits description access reset 7 spi data i/o mode select 0: 1x i/o mode select 1: 2x i/o mode select r/w 0 6 reserved / / 5:4 spi read clock delay time (valid when spi read clock delay is enabled) 00: delay 2 ns 01: delay 4 ns 10: delay 8 ns 11: delay 12 ns r/w 00 3 read start control , write 1 to start read clock (when the transfer is finished, this bit will be cleared antomatically) r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 50 2 spi write or read select bit. 0: select write 1: select read r/w 0 1:0 bytes counter high bits [1: 0] r/w 0 9 uart interface 9.1 description uart is dedicated to asynchronous serial co mmunication with fifo as data buffer for full-duplex operation. uart protocol contains a start bit, 5~8 data bits, a parity bit and a stop bit. the start bit must be 0 and the stop bit must be 1. before communication, uart operation mode must set to be the same as remote terminal, such as baud rate, number of data bits, even/odd/no parity etc. baud rate is up to 1.5mbaud and lsb first in tx/rx. two 8-level by 8 bits fifo are used to buffer data for tx and rx. 9.2 feature it is the high-speed data transmission with rate up to 1.5mbps in uart mode. 9.3 register description uart module registers address name description 79h baudrate uart baud rate register 7ah uart2ctl uart control register 7bh uairdat uart fifo data register 7ch reserved reserved 7dh uartms uart mode & fifo status register 7eh uartrqs uart drq/irq enable/status register free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 51 uart baud rate register prescale value 13 1.625 1 baud rate divisor %error divisor %error divisor %error 600 192 0.16% - - - - 1200 96 0.16% - - - - 1800 64 0.16% - - - - 2000 58 0.53% - - - - 2400 48 0.16% - - - - 3600 32 0.16% 256 0.16% - - 4800 24 0.16% 192 0.16% - - 7200 16 0.16% 128 0.16% 208 0.16% 9600 12 0.16% 96 0.16% 156 0.16% 14400 8 0.16% 64 0.16% 104 0.16% 19200 6 0.16% 48 0.16% 78 0.16% 28800 4 0.16% 32 0.16% 52 0.16% 38400 3 0.16% 24 0.16% 39 0.16% 57600 2 0.16% 16 0.16% 26 0.16% 115200 1 0.16% 8 0.16% 13 0.16% 230400 - - 4 0.16% - - 460800 - - 2 0.16% - - 750000 - - - - 2 0.00% 921600 - - 1 0.16% - - 1500000 - - - - 1 0.00% 9.3.1 baudrate (uart baud rate register, 079h) this register is used for setting uir baud rate. bits description access reset 7:0 baud rate generator, clock division r/w 00 9.3.2 uartctl (uart control register, 07ah) this register is used for selecting uart cl ock pre-scale, parity, stop bits, bits per free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 52 transmission. bits description access reset 7:6 clock pre-scale select bit 7 6 pre-scale 0 0 /13 0 1 /13 1 0 /1.625 1 1 /1 r/w 0 5:3 bit 5: stkp, stick parity bit 4: eps, even parity bit 3: pen, parity enable pen eps stkp selected parity 0 x x none 1 0 0 odd 1 1 0 even 1 0 1 logic 1 1 1 1 logic 0 r/w 0 2 stop select, if this bit is 0, 1 stop is generated in transmission. if this bit is 1 and 5 bits transmission is selected, 1.5 stop bit is generated. if this bit is 1 and 6/7/8 bits transmission is selected, 2 stop bits are generated. the receiver always checks 1 stop bit only. r/w 0 1:0 wl[1:0], bits per transmission wl1 0 bit per transmission 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits r/w 0 9.3.3 uartfdat (uart fifo data register, 07bh) this register is used for writing data to uir tx fifo or reading data from uir rx fifo. bits description access reset 7:0 uart fifo data, writing to this port will write data to uart tx fifo, reading from this port will read data from uart rx fifo r/w x free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 53 9.3.4 uartms (uart mode & fifo status register, 07dh) this register is used for displayi ng the current uart fifo status. bits description access reset 7 reserved r/w 0 6 reserved r/w 0 5 uart tx fifo full. 1: full, 0: not full. r 0 4 uart rx fifo empty. 1: empty, 0: not empty. r 1 3 reserved r/w 0 2:0 reserved r/w 0 9.3.5 uartrqs (uart drq/irq enable/status register, 07eh) this register is used for enabling uir, selecting uir drq/irq trigger threshold, and displaying current uir fifo status. bits description access reset 7 uart/ir enable, 0:disable, 1:enable r/w 0 6 fifo mode control, for all uart fifo 0: issue drq when vacancy in tx fifo or issue irq at least one data in rx fifo, 1: issue drq/irq when tx fifo is half empty or rx fifo is half full r/w 0 5 uart/ir receive error*, 0: receiving ok 1: receiving error occurs. writing 1 to this bit will clear the bit, otherwise the bit is unchanged. r/w 0 4 uart/ir rx fifo error writing 1 to this bit will clear it and reset the fifo. r/w 0 3 uart/ir tx fifo error writing 1 to this bit will clear it and reset the fifo. r/w 0 2 uart/ir rx irq pending writing 1 to the bit to clear it, while 0 unchanged. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 54 1 uart/ir irq/drq enable. 0: disable, 1: enable. r/w 0 0 uart tx fifo empty 0: not empty 1: empty r 1 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 55 10 infrared remote control interface 10.1 introduction the infrared remote control interface can only receive signal transmitted by remote controller. if the signal is coding according to one of the following three modes: toshiba 9012 code, 8 bits nec code or philips rc5 code, it can recognize them and under controlled. 10.2 features ? infrared remote control hardware decoder. ? support three infrared remote control deco de modes: toshiba 9012 code, 8 bits nec code and philips rc5 code. 10.3 register description infrared remote control module includes registers are showed as following table: irc module registers address name description 0x78 ircctl infrared remote control interface control register 0x7f ircsta infrared remote control interface state register 0x3b ircdat infrared remote control interface data register 10.3.1 ircctl (infrared remote control interface control register, 0x78) this register is used for enabling infrared remote control interface, selecting the infrared remote control coding mode and ircdat mapping type. bits description access reset free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 56 7 infrared remote control interface enable. 0: irc disable. 1: irc enable. r/w 0 6:5 infrared remote control coding mode select. 00: 9012 code 01: 8 bits nec code 10: rc5 code 11: reserved r/w 00 4 reserved / / 3 irc irq enable 0: disable 1: enable r/w 0 2:1 ircdat mapping control bit 00: ircdat mapping to irckdc 01: ircdat mapping to ircluc 10: ircdat mapping to irchuc 11: ircdat mapping to ircakdc r/w 00 0 reserved / / 10.3.2 ircsta (infrared remote control interface state register, 0x7f) this register is used for displaying irc status. bits description access reset 7 irc flag. automatically set when the irc is receiving data, automatically clear when the data has been received. 1: receiving in progress 0: receiving complete r 0 6 user code do not match pendin g bit. automatically clear when new user code matches, otherwise do not change. 0: user code match. 1: user code does not match. r 0 5 key data code verify error pend ing bit. automatically clear when new user code matches, otherwise do not change. 0: key data code verification ok. 1: key data code verification error. r 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 57 4 irc receive overflow pending bit, write 1 to this bit will clear it, otherwise don?t change. 0: irc receiving not overflow. 1: irc receiveing overflow. r/w 0 3 irc irq pending bit. write 1 to this bit will clear it, otherwise don?t change. r/w 0 2:1 reserved / / 0 irc repeat flag detect bit. write 1 to this bit will clear it, otherwise don?t change. 0: repeat code is not detected. 1: repeat code is detected. r/w 0 note: irc will request irq only when user code matches and key data code verification is ok. the mechanism avoid irq request when receive error. 10.3.3 ircluc (infrared remote cont rol low user code register, 0x3b) this register is used for storing irc low user code. bits description access reset 7:0 irc user code [7:0] r/w 0x00 10.3.4 irchuc (infrared remote control high user code register, 0x3b) this register is used for storing irc high user code. bits description access reset 7:0 irc user code [15:8] r/w 0x00 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 58 10.3.5 irckdc (infrared remote control key data code register, 0x3b) this register is used for storing irc key data code, it is read only. bits description access reset 7:0 irc key data code [7:0] r 0x00 10.3.6 ircakdc (infrared remote co ntrol anti key data code register, 0x3b) this register is used for storing irc anti key data code; it is read only for debug. bits description access reset 7:0 irc anti key data code [7:0] r 0x00 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 59 11 spdif interface 11.1 description spdif is the abbreviation of sony/philips di gital interface. the interface is primarily intended to carry stereophonic program, with a resolution of up to 20 bits per sample, an extension to 24 bits per sample being possible. please refer to spdi f standard documents for more detail information. 11.2 register description spdif module registers address name description 80h spdifctl spdif control register 81h spdifsta spdif status register 82h spdifdat spdif fifo data register 83h spdifch spdif channel status register 11.2.1 spdifctl (spdif control register, 080h) this register is used for enabling spdif and spdif drq/irq, selecting spdif drq/irq trigger threshold, and resetting spdif fifo. bits description access reset 7 spdif enable 0: disable, 1: enable. r/w 0 6:5 reserved / / 4 spdif drq trigger threshold control 0: issue drq when vacancy in tx fifo or issue irq at least one data in rx fifo, 1: issue drq/irq when tx fifo is half empty or rx fifo is half full r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 60 3 spdif drq enable 0: disable, 1: enable. r/w 0 2 spdif fifo reset 0: fifo reset valid 1: fifo reset invalid. r/w 0 1 spdif block in irq enable 0: disable, 1: enable. r/w 0 0 spdif data in irq enable 0: disable, 1: enable. r/w 0 11.2.2 spdifsta (spdif status register, 081h) this register is used for displa ying current spdif fifo status. bits description access reset 7 spdif tx fifo full. 1: full r 0 6 spdif rx fifo empty. 1: empty r 1 5 spdif block in irq pending writing 1 to this bit will clear it, while 0 unchanged. r/w 0 4 spdif data in irq pending. writing 1 to this bit will clear it, while 0 unchanged. r/w 0 3 spdif tx fifo error pending. writing 1 to this bit will clear it, otherwise unchanged. r/w 0 2 spdif rx fifo error pending. writing 1 to this bit will clear it, otherwise unchanged. r/w 0 1 spdif receive error pending. writing 1 to this bit will clear it, otherwise unchanged. r/w 0 0 spdif tx fifo empty. 0: empty, 1: not empty. r 0 11.2.3 spdifdat (spdif fifo data register, 082h) this register is used for writing data to spdi f tx fifo or reading data from spdif rx fifo. bits description access reset free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 61 7:0 spdif fifo data, write: spdif tx fifo. read: spdif rx fifo. r/w xxh 11.2.4 spdif channel status register for rx: there is 32 bits status per 192 frames transf er. all these 4-byte status bits are mapped into this register. an internal read pointer is used to point to the current byte from which data will be returned at the next read. the internal read pointer increases after a read from this register. when spdif received all 192 frames of a block, spdif irq will be issued to notice mcu to read channel status. the internal pointer will be cleared when spdif is issued. for tx: another 4 bytes status are also implemente d for transmit, which are mapped into this register also. an internal write pointer is used to point to the byte position for next write. when read from this register, the internal write pointer will be cleared to point to the first byte of tx channel status. the write pointer will move to the next byte after a write to this register. 11.2.5 spdifch (spdif channel status register, 083h) this register is used for setting spdif channel status. bits description access reset 7:0 spdif channel status r/w xxh free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 62 12 clock management unit 12.1 description ATJ331X has a low frequency oscillator, which can choose built-in source or external one. it also has a rtc (real time clock) with the alarm irq. the alarm irq can wake up the system. for protection purpose, this chip also has the watch dog circuit. it also has a timer with irq. 12.2 feature z an individual power supply pin: rtcvdd; z built-in a 32k oscillator z internal or external oscillator optional z rtc with a alarm irq which can wake up the system z 2hz irq z a timer with irq z a watch dog which can be configured irq or reset optional 12.3 register description 12.3.1 rtc control register io address mnemonic description 0x43 rtc_ctl0 rtc control 0 register 0x49 rtcregupdate rtc register update register 0x4a rtc_ctl1 rtc control 1 register 0x4b timerlb timer low byte 0x4c timermb timer middle byte 0x4d timerhb timer high byte 0x4e wdctl watch dog control register free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 63 when 43h.bit4 = 0 0x44 rtctimes rtc time second register 0x45 rtctimemin rtc time minute register 0x46 rtctimeh rtc time hour register 0x47 rtctimed rtc time day register 0x48 rtctimemon rtc time month register when 43h.bit4 = 1 0x44 rtctimeyear rtc time year register 0x45 rtcalms rtc alarm second register 0x46 rtcalmm rtc alarm minute register 0x47 rtcalmh rtc alarm hour register 0x48 rtcrdm rtc random access register note: the following register marked by rtcvdd, means ?the register?s power is supplied by rtcvdd. and the register is reset by rtcvdd_ok.? and that marked by vdd, means ?the register?s power is supplied by rtcvdd. and the register is reset by vdd_rst.? 12.3.1.1 rtc_ctl0 (rtc control 0 register. 0x43) (rtcvdd) bits bit mnemonic description access reset 7 cal_en calendar enable 0: sisable 1: enable r/w 0 6 en_almpd alarm pending enable. 0: disable. the alarm pending bit is disabled. the pending bit is not set when alarm is occoured 1: enable. r/w 0 5 test_en test enable 0: disable 1: enable. the rtc?s losc is changed to hosc r/w 0 4 page_sel register page select register 0: io registers ?44h-48h? are rtc time register. 1: io registers ?44h-48h? are rtc alarm register, random register and rtc time year register. r/w 0 3 ext_losc_en external losc enable 0: disable r/w 1 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 64 1: enable 2 cal_clk_select calendar clock select 0: select ilosc 1: select elosc r/w 0 1 leap year rtc leap year bit 1: leap year 0: not leap year r 1 0 alm_ip alarm irq pending bit. writing 1 to this bit will clear it . r/w 0 note: the cal_en bit must be disabled when th e rtc time register being written, and all rtc time registers must be written before cal_en is enabled when the timeis set, otherwise error will occurs. 12.3.1.2 rtctimes (rtc time second register, 0x44) (rtcvdd) bits bit mnemonic description access reset 7:6 - reserved - - 5:0 time_sec calendar time second[5:0] r/w 0 12.3.1.3 rtctimemin (rtc time minute register, 0x45) (rtcvdd) bits bit mnemonic description access reset 7:6 - reserved - - 5:0 time_min calendar time minute[5:0] r/w 0 12.3.1.4 rtctimeh (rtc time hour register, 0x46) (rtcvdd) bits bit mnemonic description access reset 7:5 - reserved - - 4:0 time_hour calendar time hour[4:0] r/w 0 12.3.1.5 rtctimed (rtc time day register, 0x47) (rtcvdd) bits bit mnemonic description access reset 7:5 - reserved - - 4:0 time_day calendar time day[4:0] r/w 01 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 65 12.3.1.6 rtctimemon (rtc time month register, 0x48) (rtcvdd) bits bit mnemonic description access reset 7:4 - reserve - - 3:0 time_mon calendar time month[3:0] r/w 01 12.3.1.7 rtctimeyear (rtc time year register, 0x44) (rtcvdd) bits bit mnemonic description access reset 7 - reserved - - 6:0 time_year calendar time year[6:0] r/w 0 12.3.1.8 rtcalms (rtc alarm second register, 0x45) (rtcvdd) bits bit mnemonic description access reset 7:6 - reserved - - 5:0 alm _sec alarm second[5:0] r/w 0 12.3.1.9 rtcalmm (rtc alarm minute register, 0x46) (rtcvdd) bits bit mnemonic description access reset 7:6 - reserved - - 5:0 alm _min alarm minute [5:0] r/w 0 12.3.1.10 rtcalmh (rtc alarm hour register, 0x47) (rtcvdd) bits bit mnemonic description access reset 7:5 - reserved - - 4:0 alm _hour alarm hour [4:0] r/w 0 12.3.1.11 rtcrdm (rtc random access register, 0x48) (rtcvdd) bits bit mnemonic description access reset 7:0 random these bits can be accessed by cpu freely. r/w 0 12.3.1.12 rtcregupdate (rtc register update control register,0x49) (rtcvdd) bits bit description access reset free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 66 mnemonic 7:0 update the rtcvdd register update control register. when writing the rtc registers (except rtcregupdate register or bit ?alm_ip?), the rtc registers? values will not be updated immediately. the value is written to backup registers (in vdd) first. just when writing rtcregupdate register a5h, the rtcvdd registers? values are update with the backup registers? value. rtcregupdate register is automatically reset as 5ah after the rtcvdd register is update. note: 1. do not write rtcvdd registers when this register value is a5h. 2. when writing the bit ?alm_ip?, it will take effect immediately. no need to write this register. r/w 0x5a 12.3.1.13 rtc_ctl1 (rtc control 1 register. 0x4a) (vdd) bits bit mnemonic description access reset 7 2hz_en 2hz irq enable 0: disable 1: enable r/w 0 6 timer_en rtc timer enable 0: disable 1: enable r/w 0 5 clk_sel watch dog, 2hz, timer?s clock select bit: 0: pmu_clk_div 1: elosc r/w 0 4:2 -- reserved / 1 2hz_ip 2hz irq pending bit writing 1 to this bit will clear it . r/w 0 0 timer_ip timer irq pending bit writing 1 to this bit will clear it . r/w 0 12.3.1.14 timerlb (timer low byte, 0x4b) (vdd) bits bit mnemonic description access reset 7:0 timerlb low byte of timer register timer is a down counter with losc as clock. when the counter overflow, timer_ip will occur. r/w x free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 67 timer_ip = [1/(time bit[23:0]+1)] *flosc 12.3.1.15 timermb (timer middle byte, 0x4c) (vdd) bits bit mnemonic description access reset 7:0 timermb middle byte of losc divider register r/w x 12.3.1.16 timerhb (timer high byte, 0x4d) (vdd) bits bit mnemonic description access reset 7:0 timerhb high byte of timer register r/w x 12.3.1.17 wdctl (watch dog control register, 0x4e) (vdd) bits bit mnemonic description access reset 7 wd_en watch dog timer enable, when wd timer is enabled and the wd timer overflows, either an internal reset (wdrst-) is generated to force the system into reset status and then reboot, or an irq is sent to cpu. r/w 0 6:4 clk_sel watch dog timer clock select, wdcks clock selected watch dog length the watch dog?s overflow value is 180. 000 1khz 176 ms 001 512hz 352 ms 010 256hz 703ms 011 128hz 1.4 s 100 64hz 2.8s 101 32hz 5.6 s 110 16hz 11.2s 111 8hz 22.5 s r/w 010 3 clr clear bit, write 1 to clear wd timer, cleared automatically w 0 2 mode_sel watchdog irq or reset- select. 0: sent reset when dog timer overflows 1: sent irq when dog timer overflows r/w 0 1 wd_flag watch dog overflow flag 1: means wd reset or irq ever occurred. writing 1 to this bit clears it. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 68 0:not occurred this bit is reset by powerok signal 0 - reserved / x 12.3.2 hosc/pll 12.3.2.1 hfcctl (high frequency crystal control register, 040h) bits description access reset 7 high frequency crystal oscillator enable. 0: disable, 1: enable r/w 0 6 power ok status. 0: power on, 1: power on finished. r 0 5:4 reserved / / 3:2 high frequency crystal oscillator gmmin select bits 00 gain=3.2 01 gain=6.1 10 gain=8.0 11 gain=10.1 r/w 01 1:0 reserved / / 12.3.2.2 ck48mctl (ck48mctl control register, 042h) bits description access reset 7: 6 reserved r/w 0 5 ck48m enable 0: disable 1: enable r/w 0 4:0 reserved. / / 12.3.2.3 mcupll (mcu pll control, 28h) bits description access reset 7 mcu pll enable 0: disable 1: enable r/w 0 6:2 mcu pll output select r/w 00000 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 69 0 0 0 x x 12mhz 0 0 1 0 0 16mhz 0 0 1 0 1 20mhz 0 0 1 1 0 24mhz 0 0 1 1 1 28mhz 0 1 0 0 0 32mhz 0 1 0 0 1 36mhz 0 1 0 1 0 40mhz 0 1 0 1 1 44mhz 0 1 1 0 0 48mhz 0 1 1 0 1 52mhz 0 1 1 1 0 56mhz 0 1 1 1 1 60mhz 1 0 0 0 0 64mhz 1 0 0 0 1 68mhz 1 0 0 1 0 72mhz 1 0 0 1 1 76mhz 1 0 1 0 0 80mhz 1 0 1 0 1 84mhz 1 0 1 1 0 88mhz 1 0 1 1 1 92mhz 1 1 0 0 0 96mhz 1 1 0 0 1 100mhz 1 1 0 1 0 104mhz 1 1 0 1 1 108mhz 1 1 1 0 0 112mhz 1 1 1 0 1 116mhz 1 1 1 1 0 120mhz 1 1 1 1 1 124mhz 1:0 reserved / / 12.3.3 clock selection unit 12.3.3.1 mcsr1 (module clock select register 1, 2bh) bits description access reset free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 70 7 uart controller clock select 0 dc 1 ck48m r/w 0 6 spdif controller clock select 0 dc 1 ck48m r/w 0 5:4 spi controller clock select 0 x dc 1 0 hosc 1 1 mcu pll r/w 00 3 i2c controller clock select 0 dc 1 hosc r/w 0 2:0 reserved / / 12.3.3.2 mcsr2 (module clock select register 2, 2ch) bits description access reset 7:2 reserved / / 1:0 dma1 and dma2 clock select 0 0 losc 0 1 hosc 1 0 mcu pll 1 1 dc r/w 11 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 71 13 a/d d/a and headphone driver 13.1 introduction the d/a a/d module includes a sigma-delt a dac, a sigma-delta adc which supports microphone/fm/line input. both dac and adc support 48k/44.1k/32k/24k/22.05k/16k/12k/11.025k/8k sample rate. its on-chip 20mw power amplifier can support to drive 32/16ohm earphone. 13.2 feature ? build in stereo 20-bit sigma-delta dac ? build in stereo 21-bit sigma-delta adc ? build in stereo headphone driver ? support sample rate of 8k/12k/11.025k/16k/22.05k/24k/32k/44.1/48khz ? support microphone/fm/line input to adc ? max output: 220mw@16ohm 13.3 adda analog diagram free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 72 + mux adc_a & adc_d adc_en dac_mut e micin l/r mic_en en fm_en en en mixer&pa_en mic_mix_en fm_mix_en fminl /r aoutl/r pa_volume adc_input_sel mic_gain fm_gain lpf_gain dac_a en dac_a_en en a/d lpf vro_en vref vro vro_sense 13.4 dac the audio dac is an on-chip sigma-delta modulator, a 16 bit high performance dac is composed of it. the dac interface support 8-leve l play back fifo (16 x 16bits pcm data for l/r channel) and variable sample rates, such as 48k/44.1k/32k/24k/22.05k/16k /12k/11.025k/8khz. an on-chip pll2 is used to generate 22.5792mhz from 24mhz to support 44.1k/22.05k/11.025khz with 256fs free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 73 clock for over-sampling, while 24mh z supports 48k/32k/24k/16k/12k/8khz with 256fs for over-sampling. 13.5 adc the audio adc is an on-chip sigma-delta analog-to-digital converter, which support input from mic or external fm or linein. the adc interface support 16-level fifo (16 x 16bits x 2 pcm data for l/r channel) and variable sample rates, such as 48k/44.1k/32k/24k/22.05k/16k /12k/11.025k/8khz. an on-chip pll2 is used to generate 22.5792mhz from 24mhz to support 44.1k/22.05k/11.025khz with 256fs clock for over-sampling, while 24mh z supports 48k/32k/24k/16k/12k/8khz with 256fs for over-sampling. free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 74 14 gpio/multifunction 14.1 description there are totally 45 gpios which can be used as output/input separately or simultaneously. each gpio is used as a mult ifunction with other function pin. set the relevant register before using the needed function. 14.2 feature ? 45 gpios which can be used as output/i nput separately or simultaneously ? different level of static driving current and dynamic driving capacity ? maximum frequency of gpios up to 30mhz ? flexible alternation of multifunctio n, especially in sd/mmc/ms module 14.3 register description gpio/mfp includes registers as following: address name description 0xee mfpsel mfp select register 0xed gpioaouten gpioa output enable 0xef gpioainen gpioa input enable 0xf0 gpioadat gpioa data 0xf1 gpiobouten gpiob output enable 0xf2 gpiobinen gpiob input enable 0xf3 gpiobdat gpiob data 0xf4 gpiocouten gpioc output enable 0xf5 gpiocinen gpioc input enable 0xf6 gpiocdat gpioc data 0xf7 gpiodouten gpiod output enable 0xf8 gpiodinen gpiod input enable 0xf9 gpioddat gpiod data free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 75 0xfa gpioeouten gpioe output enable 0xfb gpioeinen gpioe input enable 0xfc gpioedat gpioe data 0xfd gpiofouten gpiof output enable 0xfe gpiofinen gpiof input enable 0xff gpiofdat gpiof data 14.3.1 mfpsel (mfp select register, 0eeh) bits description access reset 7 gpio_a1, gpio_a[4:3], gpio_ c[1:0] and ice multifunction 0: ice port 1: gpio_a1, gpio_a [4:3], gpio_c[1:0] r/w 0 6 gpiob7 and rb2- multifunction 0: rb2- 1: gpiob7 r/w 0 5 gpiob6 and rb1- multifunction 0: rb1- 1: gpiob6 r/w 0 4 gpiob5 and cle multifunction 0: cle 1: gpiob5 r/w 0 3 gpiob4 and ale multifunction 0: ale 1: gpiob4 r/w 0 2 gpiob3 and mwr- multifunction 0: mwr- 1: gpiob3 r/w 0 1 gpiob2 and mrd- multifunction 0: mrd- 1: gpiob2 r/w 0 0 gpiod[7:0] and data multifunction 0: data bus 1: gpiod[7:0] r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 76 14.3.2 gpioaouten (gpio_a output enable register, 0edh) bits description access reset 7 gpio_a7 output enable, 0: disable, 1: enable. r/w 0 6 gpio_a6 output enable, 0: disable, 1: enable. r/w 0 5 gpio_a5 output enable, 0: disable, 1: enable. r/w 0 4 gpio_a4 output enable, 0: disable, 1: enable. r/w 0 3 gpio_a3 output enable, 0: disable, 1: enable. r/w 0 2 gpio_a2 output enable, 0: disable, 1: enable. r/w 0 1 gpio_a1 output enable, 0: disable, 1: enable. r/w 0 0 gpio_a0 output enable, 0: disable, 1: enable. r/w 0 14.3.3 gpioainen (gpio_a input enable register, 0efh) bits description access reset 7 gpio_a7 input enable, 0: disable, 1: enable. r/w 0 6 gpio_a6 input enable, 0: disable, 1: enable. r/w 0 5 gpio_a5 input enable, 0: disable, 1: enable. r/w 0 4 gpio_a4 input enable, 0: disable, 1: enable. r/w 0 3 gpio_a3 input enable, 0: disable, 1: enable. r/w 0 2 gpio_a2 input enable, 0: disable, 1: enable. r/w 0 1 gpio_a1 input enable, 0: disable, 1: enable. r/w 0 0 gpio_a0 input enable, 0: disable, 1: enable. r/w 0 14.3.4 gpioadat (gpio_a data outp ut/input register, 0f0h) bits description access reset 7:0 output/input data[7:0] r/w xxh free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 77 14.3.5 gpiobouten (gpio_b output enable register, 0f1h) bits description access reset 7 gpio_b7 output enable, 0: disable, 1: enable. r/w 0 6 gpio_b6 output enable, 0: disable, 1: enable. r/w 0 5 gpio_b5 output enable, 0: disable, 1: enable. r/w 0 4 gpio_b4 output enable, 0: disable, 1: enable. r/w 0 3 gpio_b3 output enable, 0: disable, 1: enable. r/w 0 2 gpio_b2 output enable, 0: disable, 1: enable. r/w 0 1 gpio_b1 output enable, 0: disable, 1: enable. r/w 0 0 gpio_b0 output enable, 0: disable, 1: enable. r/w 0 14.3.6 gpiobinen (gpio_b input enable register, 0f2h) bits description access reset 7 gpio_b7 input enable, 0: disable, 1: enable. r/w 0 6 gpio_b6 input enable, 0: disable, 1: enable. r/w 0 5 gpio_b5 input enable, 0: disable, 1: enable. r/w 0 4 gpio_b4 input enable, 0: disable, 1: enable. r/w 0 3 gpio_b3 input enable, 0: disable, 1: enable. r/w 0 2 gpio_b2 input enable, 0: disable, 1: enable. r/w 0 1 gpio_b1 input enable, 0: disable, 1: enable. r/w 0 0 gpio_b0 input enable, 0: disable, 1: enable. r/w 0 14.3.7 gpiobdat (gpio_b data outp ut/input register, 0f3h) bits description access reset free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 78 7:0 output/input data[7:0] r/w xxh 14.3.8 gpiocouten (gpio_c output enable register, 0f4h) bits description access reset 7 gpio_c7 output enable, 0: disable, 1: enable. r/w 0 6 gpio_c6 output enable, 0: disable, 1: enable. r/w 0 5 gpio_c5 output enable, 0: disable, 1: enable. r/w 0 4 gpio_c4 output enable, 0: disable, 1: enable. r/w 0 3 gpio_c3 output enable, 0: disable, 1: enable. r/w 0 2 gpio_c2 output enable, 0: disable, 1: enable. r/w 0 1 gpio_c1 output enable, 0: disable, 1: enable. r/w 0 0 gpio_c0 output enable, 0: disable, 1: enable. r/w 0 14.3.9 gpiocinen (gpio_c input enable register, 0f5h) bits description access reset 7 gpio_c7 input enable, 0: disable, 1: enable. r/w 0 6 gpio_c6 input enable, 0: disable, 1: enable. r/w 0 5 gpio_c5 input enable, 0: disable, 1: enable. r/w 0 4 gpio_c4 input enable, 0: disable, 1: enable. r/w 0 3 gpio_c3 input enable, 0: disable, 1: enable. r/w 0 2 gpio_c2 input enable, 0: disable, 1: enable. r/w 0 1 gpio_c1 input enable, 0: disable, 1: enable. r/w 0 0 gpio_c0 input enable, 0: disable, 1: enable. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 79 14.3.10 gpiocdat (gpio_c data outp ut/input register, 0f6h) bits description access reset 7:0 output/input data[7:0] r/w xxh 14.3.11 gpiodouten (gpio_d output enable register, 0f7h) bits description access reset 7 gpio_d7 output enable, 0: disable, 1: enable. r/w 0 6 gpio_d6 output enable, 0: disable, 1: enable. r/w 0 5 gpio_d5 output enable, 0: disable, 1: enable. r/w 0 4 gpio_d4 output enable, 0: disable, 1: enable. r/w 0 3 gpio_d3 output enable, 0: disable, 1: enable. r/w 0 2 gpio_d2 output enable, 0: disable, 1: enable. r/w 0 1 gpio_d1 output enable, 0: disable, 1: enable. r/w 0 0 gpio_d0 output enable, 0: disable, 1: enable. r/w 0 14.3.12 gpiodinen (gpio_d input enable register, 0f8h) bits description access reset 7 gpio_d7 input enable, 0: disable, 1: enable. r/w 0 6 gpio_d6 input enable, 0: disable, 1: enable. r/w 0 5 gpio_d5 input enable, 0: disable, 1: enable. r/w 0 4 gpio_d4 input enable, 0: disable, 1: enable. r/w 0 3 gpio_d3 input enable, 0: disable, 1: enable. r/w 0 2 gpio_d2 input enable, 0: disable, 1: enable. r/w 0 1 gpio_d1 input enable, 0: disable, 1: enable. r/w 0 0 gpio_d0 input enable, 0: disable, 1: enable. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 80 14.3.13 gpioddat (gpio_d data outp ut/input register, 0f9h) bits description access reset 7:0 output/input data[7:0] r/w xxh 14.3.14 gpioeouten (gpio_e [4:0] ou tput enable register, 0fah) bits description access reset 7:6 0 0 reserved 0 1 reserved 1 0 gpioe4 output losc. 1 1 gpioe4output hosc. if bit7 is set, gpioe4 can only output osc. r/w 0 5 reserved r/w 0 4 gpio_e4 output enable, 0: disable, 1: enable r/w 0 3 gpio_e3 output enable, 0: disable, 1: enable r/w 0 2 gpio_e2 output enable, 0: disable, 1: enable r/w 0 1 gpio_e1 output enable, 0: disable, 1: enable r/w 0 0 gpio_e0 output enable, 0: disable, 1: enable r/w 0 14.3.15 gpioeinen (gpio_e [4:0] inpu t enable register, 0fbh) bits description access reset 7:5 reserved / / 4 gpio_e4 input enable, 0: disable, 1: enable r/w 0 3 gpio_e3 input enable, 0: disable, 1: enable r/w 0 2 gpio_e2 input enable, 0: disable, 1: enable r/w 0 1 gpio_e1 input enable, 0: disable, 1: enable r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 81 0 gpio_e0 input enable, 0: disable, 1: enable r/w 0 14.3.16 gpioedat (gpio_e [4:0] data output/input register, 0fch) bits description access reset 7:5 reserved / / 4:0 output/input data[4:0] r/w xxh 14.3.17 gpiofouten (gpio_f [7:0] output enable register, 0fdh) bits description access reset 7 gpio_f7 output enable, 0: disable, 1: enable r/w 0 6 gpio_f6 output enable, 0: disable, 1: enable r/w 0 5 gpio_f5 output enable, 0: disable, 1: enable r/w 0 4 gpio_f4 output enable, 0: disable, 1: enable r/w 0 3 gpio_f3 output enable, 0: disable, 1: enable r/w 0 2 gpio_f2 output enable, 0: disable, 1: enable r/w 0 1 gpio_f1 output enable, 0: disable, 1: enable r/w 0 0 gpio_f0 output enable, 0: disable, 1: enable r/w 0 14.3.18 gpiofinen (gpio_f [7:0] inpu t enable register, 0feh) bits description access reset 7 gpio_f7 input enable, 0: disable, 1: enable r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 82 6 gpio_f6 input enable, 0: disable, 1: enable r/w 0 5 gpio_f5 input enable, 0: disable, 1: enable r/w 0 4 gpio_f4 input enable, 0: disable, 1: enable r/w 0 3 gpio_f3 input enable, 0: disable, 1: enable r/w 0 2 gpio_f2 input enable, 0: disable, 1: enable r/w 0 1 gpio_f1 input enable, 0: disable, 1: enable r/w 0 0 gpio_f0 input enable, 0: disable, 1: enable r/w 0 14.3.19 gpiofdat (gpio_f [7:0] data output/input register, 0ffh) bits description access reset 7:0 output/input data[7:0] r/w xxh 14.3.20 gpioe0_vccoutsr (gpioe0_vc cout select register, 088h) bits description access reset 7:2 reserved / / 1 vccout is used for fm power supply. 0: vccout pin floating, no power out 1: vccout=2.89v, there is a ldo from vcc to vccout. if there is a capacitance at vccout, you should wait a moment after setting this bit to 1. r/w 0 0 gpioe0 as a multi pin, it can us e as vccout for fm power supply. 0: gpioe0 is used as ms_bs or gpioe0 1: gpioe0 is used as vccout r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 83 15 pwm 15.1 introduction pwm output module is embedded in ATJ331X, in the purpose of controlling the external backlight ic conveniently. it supplies several output frequency and va riable duty occupancy for adjusting the intensity of the lcd backlight. 15.2 feature ? 2 selected sources :24m or 32k; ? frequency dividing maximum to 4; ? available frequency in end are 94k, 47k, 24k, 12k, 1k, 500hz, 250hz, 125hz; ? 8 levels duty occupancy adjusting; ? high level or low level active selecting. 15.3 register description address name description afh pwmctl pwm control register 15.3.1 pwmctl (pwm control register, afh) bits description access reset 7 pwm enable. 0: disable the pwm module 1: enable the pwm module note: when enableing the pwm module, the gpioc0 is used as the pwm pin, if the mofule disabled, the gpioc0 is used as gpioc0 or i2c_sck r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 84 6 source select. 0: choose 24mhz as dividing source 1: choose 32khz as dividing source r/w 1 5:4 frequency divide. choose the divisor for dividing dividing source 94k 1k 00: /1 94k 1k 01: /2 47k 500hz 10: /4 24k 250hz (recommened) 11: /8 12k 125hz r/w 10 3 active polarity select. 0: pwm is high level active 1: pwm is low level active r/w 0 2:0 active duty occupancy. 000: 0/8 001: 1/8 010: 2/8 011: 3/8 100: 4/8 101: 5/8 110: 6/8 111: 7/8 r/w 100 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 85 16 power management unit 16.1 introduction ATJ331X integrates a comprehensive power supply subsystem, including the following features: z supports two battery types: 1-cell alkaline/n imh and li-ion battery, selected by pwrmb pin. z two integrated dc-dc converters: vdd and vcc. vdd can work in boost mode from 1-cell alkaline/nimh, or work in buck mode from li-ion cell, which supplies core power. the other can only work in boost mode fr om 1-cell alkaline/nimh, which supplies i/o power. z five linear regulators supply power directly from dc5v or li-ion cell. the outputs are vcc, vdd, avcc, avdd and fm_vccout. z linear battery charger for li-ion cell. z battery voltage monitor, system monitors for temperature and wire-controller. z ATJ331X power supply is designed to offer maximum flexibility and performance, while minimizing external component requirements. 16.2 function block diagram figure 16-2-1 and figure 16-2-2 show the two output s vcc and vdd for the two supported battery types. table 16-2-1 lists power su pply modes in which vcc/vdd how to work. the figures and the table can be used to un derstand how to set hardware connection relate to which subsystems, but they are no t intended to be a complete architecture description. free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 86 figure 16-2-1 li-ion supply peripheral connection figure 16-2-2 1-cell alkaline/nimh supply peripheral connection free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 87 table 16-2-1 power supply mode description pwrmb dc5v>4.3v dcdc_vcc vcc regulator dcdc_vdd vdd regulator 1 alkaline/nimh, 2 inductor 1 n y n y n 1 alkaline/nimh, 1 inductor for vcc 1 n y n n y li-ion, 1 inductor for vdd 0 n n y y n li-ion, 2 regulators 0 n n y n y usb or adapter, 2 regulators x y n y n y 16.3 dc-dc converters the dc-dc converter efficiently scales battery voltage to the required supply voltages. the dc-dc converters include several advanced features: z flexible battery support for either 1-cell alkaline/nimh or li-ion batteries z synchronization dc-dc converter architecture z work in pulse frequency modulation (p fm) or pulse-width modulation (pwm) automatically for different load current. 16.3.1 dc-dc accurate and maximum output current the output voltages are highly precise within 2%; they provide large currents with a significantly small dropout voltage within 5%. dc-dc maximum output current block name loading vcc dc-dc(boost mode) bat=1.0v, 85ma @ vcc=3.1v dropping 5% bat=1.2v, 120ma @ vcc=3.1v dropping 5% boost mode bat=1.0v, 60ma @ vdd=1.7v dropping 5% bat=1.2v, 80ma @ vdd=1.7v dropping 5% vdd dc-dc buck mode bat=3.4v, 80ma @ vdd=1.7v dropping 5% free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 88 16.3.2 dc-dc converter efficiency typical efficiency of the dc-dc conver ters under nominal condition is 80%. 16.4 linear regulators ATJ331X integrates five linear regulators; they generate vcc, vdd, avcc, avdd and fm_vccout. linear regulators are typically used when the system is powered from a 5-v supply or usb. 16.4.1 regulators output voltage set the output voltage setting of vcc and vdd linear regulators is the same as dc-dc converter. avcc is typically set once during system initialization, avcc=2.95v the output voltage of avcc linear regulator changes follows vcc setting. fm_vccout is enabled by setting register. the voltage is 2.89v. 16.4.2 regulators accurate and maximum output current the output voltages are highly precise within 2%. they provide large currents with a significantly small dropout voltage within 5%. regulators maximum output current block name loading vcc regulator bat=3.4v or dc5v=4.5v, 200ma @ vcc=3.1v, decreasing 5% vdd regulator vcc=3.1v, 80ma @ vdd=1.7v, decreasing 5% avcc regulator vcc=3.1v, 50ma @ avcc, decreasing 2% fm_vccout vcc=3.1v, 35ma @ fm_vccout, decreasing 5% free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 89 16.5 li-ion cell charger some products in ATJ331X family integrate the charging for li-ion battery from a 5-v source connected to the dc5v pin. the battery charger is essentially a linear regulator that has current and voltage limits. charge current is software-programmable. user can enable charger by setting register. li-ion batteries can be charged as low as of 1c, 500 ma, or the dc5v current limit. usb charging is typically limited to 500 ma or less to meet compliance requirements. typical charge times for a li-ion battery are 2 to 3 hours with >90% of the charge delivered. there is 3 phases through all the charging proc ess: when battery voltage is between 3.0v to 4.2v, the charging current is set by chg cont rol register, this phase is called constant current charging phase (cc for short). at this ph ase, the charging current is constant and the voltage of battery is going up slowly. when battery voltage is below 3.0v,the charging current is 1/10 of cc, this phase is called trickle charging phase or pre-charge. you can mask trickle charging by chg control register bit4=1. when battery voltage gets to 4.2v, the battery voltage will be constant, and the charging current is reduced gradually, this phase is called constant vo ltage phase (cv for short). the battery charge voltage is limited to 4.2 v when the reference voltage is 1.5v. if the reference voltage is changed, the limited voltage is changed correspondingly. the li-ion charge is typically stopped when the charging current drops below 7.5% of the charge current set by chg control register. the register chg control register includes controls for the maximum charge current and the register chg detect register includes controls for the stop charge current. while the charger is delivering the current greater than the stop charge limit, the register chg status is high. when the charging is complete, the bit goes low. one can programmatically monitor the battery voltage by using the batadc. the charger has its own voltage limiting that operates inde pendently of the batadc. but monitoring the battery voltage during the charge might be helpful for reporting the charge progress. the battery charger is capable of generating a large amount of heat within ATJ331X, especially at the current above 400 ma. th e dissipated power can be estimated: (5v ? battery voltage) * current. at a max current (500ma) and a 3-v battery, the charger can dissipate 1 w. the lradc2 can be used to monitor the batt ery temperature or chip temperature. to ensure that the system operates correctly, it should be monitored at every 100 ms. it would be a good practice to check the output data of lradc2 for two consecutive checks. if the battery temperature exceeds 45 c, then the batt ery charge current must be reduced or the charger must be stopped. free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 90 16.6 a/d converters there is a low resolution 7 bit a/d for battery monitor and temperature monitor, the input voltage range of which is 1.4 to 4.4v at vbat pin in li-ion supply mode, 0.7 to 2.2v at vbat pin in 1-cell alkaline supply mode, an d 0.7 to 2.2v at lradc2 pin. there is a low resolution 6 bit a/d for wire cont rol. the input voltage range of which is 0 to avcc at lradc1 pin.the a/d converter?s working frequency is 64hz default. the impedance between ba t(or lradc1 or lradc2) and gnd is up to m ? the output data of batadc can be ca lculated as the following formula: li-ion batadc: one lsb= 2 7 4 . 1 4 . 4 * 5 . 1 vref , when battery voltage= vbat, adc?s data is n= 5 . 1 * 4 . 1 4 . 4 5 . 1 * 4 . 1 2 7 vref vref vbat , in which vref is the reference voltage tested. for example, if vref=1.500v, then 1lsb=23.44mv, and the corresponding data from 1.4v to 1.42344v are 00h, the corresponding data from 1.42344v to 1.44688v are 01h/ 1aaa batadc: one lsb= 2 7 7 . 0 2 . 2 * 5 . 1 vref , when battery voltage=vbat, adc?s data is n= 5 . 1 * 7 . 0 2 . 2 5 . 1 * 7 . 0 2 7 vref vref vbat , in which vref is the reference voltage tested. for example, if vref=1.500v, then 1lsb=11.72mv, and the corresponding data from 0.7v to 0.7119v are 00h, the corresponding data from 0.71172v to 0.72344v are 01h. lradc1/lradc3/lradc4/lradc5: free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 91 one lsb= 2 6 avcc , when input voltage=v, the corresponding adc is n= 2 6 avcc v . for example, if avcc=2.87v then 1lsb=44.84mv, and the corresponding data from 0v to 0.04484v are 00h, and the corresponding data from 0.04484v to 0.8968v are 01h. lradc1/lradc3/lradc4/lradc5 use 1 adc at different time, and lradc3 and gpio_f5 multiplexes, lradc4 and gpio_f6 mult iplexes, lradc5 and gpio_f7 multiplexes. 16.7 programmable registers 16.7.1 system_ctl_rtcvdd, (system control register, 0a5h) (rtcvdd) system and standby control bits description access reset 7:6 syson key pressing length setting: 00: 60ms < t < 2s, set short-press status flag; t>=2s, system startup or send long-press status flag; 01: 60ms < t < 3s, send short-press status flag; t>=3s, system startup or send long-press status flag; 10: 60ms < t < 4s, send short-press status flag; t>=4s, system startup or send long-press status flag; 11: 60ms < t < 5s, send short-press status flag; t>=5s, system startup or send long-press staus flag; note: please refer to reg[0a6h] for flag bit. r/w 01 5 lb_ to standby enable in li-ion mode 0: disable, shield low power to standby function; 1: enable, enable low power to standby function; the battery voltage for low power to standby can be set via reg[a5h.bit4:3]. r/w 1 4:3 lb (low battery) voltage setting li-ion 00 2.7v ***01 3.0v 1x 3.3v r/w 01 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 92 2 vcc/vdd ldo over-current protection enable; 0: disable 1: enable r/w 1 1 vcc/vdd too-low-voltage protection enable; 0: disable 1: enable effective to lithium battery, but not for single power. for hard switch solution, if the system cannot start in case of fast-speed power on and power off, try to shield the bit to 0. r/w 1 0 reg_enpmu: 0: disable vcc/vdd 1: enable vcc/vdd when the status is turn from s3 to s1, the bit is set as 1. r/w 1 note: after the writing operation over the registers under rtcvdd, it is necessary to wait 3 z80clk cycle as well as 4 low frequency cycle for the real writing-in and the written value then can be read. 16.7.2 system_ctl_vdd (system set register, 0a6h) system set register system contril vdd, including long/short pre ssing flag, single-power standby setting, efuse enable setting and register switch page setting. bits description access reset 7 short-press status flag: 0: no short-press status flag, sy son key not been pressed in short time. 1: has short-press status, syson ke y been pressed in short time, and the time is within the setting value. write 1 to this bit to clear it. note (for design): only after the bit is cleared to 0 and there is key, the next detection can be carried out an d the next next status can only be sent when the time requirement has be met. it is the same as that of interrupt design of key. (for software): in hard switch solution, after the running of brom, it is necessary to write 1 to the bit and clear it to 0 for once in order to avoid the error of short key pressing when hard switch is cut off. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 93 6 long-press status flag: 0: no long-press status flag, syson key not been pressed for long time. 1: has long-press status status, syson key been pressed for long time and the time exceeds the setting value. if the key is not up, do not re-timing. one key status display, read-only. r x 5:4 reserved r/w 0 3 reg_iovdd_r: whether iovdd 300kohm?s pull-down resistor controls effectively; 0: pwrmb=1, control iovdd for no 300kohm pull-down. 1: pwrmb=1, control iovdd for 300kohm pull-down. r/w 1 2 iovdd status: 0: iovdd is low; 1: iovdd is high. r x 1:0 register switch page control 00: can operate page0 register before switch page 01: can operate page1 register after switch page 10: can operate page2 register after switch page 11: can operate page3 register after switch page (for cmu module) r/w 00 note: lb/lbnmi will be effective when batadc is enabled. 16.7.3 voutctl (dc-dc & regulator output voltage control register, page0_089h) the vout control resister controls the outp ut voltage of vcc/vdd dc-dc converters and regulators. bits description access reset 7 pwrmb, refelecting power mode. 1----1 alkaline/nimh 0----li-ion this bit is read only, which depend on pin pwrmb. the default is 0. for signal power solution, a 400koh m resistor shall be added between dc5v and vbat, otherwise, if there is no battery connected, it will be regarded as pwrmb=0, li-ion mode. r x free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 94 6:4 vcc voltage level select 111 3.3v 110 3.2v 101 3.1v 100 3.0v 011 2.9v 010 2.8v 001 2.7v 000 2.6v vcc is typically set to 3.1v once during system initialization; it remains unchanged until operating these 3 bits. in test mode, the power-up is defaulted at 2.6v, vcc= 2.6v (avcc =2.45v) (digital). r/w 101 3:1 vdd(dc-dc & regulator) vo ltage coarse control 000 1.3v 001 1.4v 010 1.5v 011 1.6v 100 1.7v 101 1.8v 110 1.9v 111 2.0v vdd is typically set to 1.7v once during system initialization; it remains unchanged until operating th ese 3 bits. user can set vdd at a lower voltage (1.6v) at light loading to reduce power dissipation. avdd voltage set to be slight lower than vdd, 100mv; in test mode, power-up is defaulte d at 1.3v, vdd=1.3v, avdd =1.2v. r/w 100 0 vdd (dc-dc & regulator) voltage fine control (one control level=50mv); 0: disable; 1: enable r/w 0 16.7.4 lbnmi & adcirq (lbnmi & adcirq control register, page0_08ch) pmu?s nmi and irq to set registers. free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 95 bits description access reset 7 lradc1 irq enable. 0: disable, shield lradc1 interrupt function; 1: enable, enable lradc1 interrupt function; lradc1?s interrupt voltage can be avcc, or can be lower than 0.9*avcc, decided via reg [8ch.bit6]. r/w 0 6 lradc1 irq threshold. 0: low, 0.9*avcc. when the voltage of lradc1 pin is lower than 0.9*avcc, if lradc1 irq enable d, the ioreg [8dh.bit6] will be pended. 1: high, avcc. when the voltage of lradc1 pin is lower than avcc, if lradc1 irq enabled, the ioreg [8dh.bit6] will be pended. r/w 0 5 lradc1 irq pending. writing 1 will clear this bit. when wire-control iuput is lower than irq threshold voltage, the pending bit is set to 1. r/w 0 4 lbnmi_ enable, low power alarm enable bit. 0: disable, shield low power alarm function. 1: enable, enable low pwer alarm function. the bit shall be used together with batadc?s enable bit and only when batadc enabled, the bit could be 1. moreover, only when reg [04h.bit1]=1, low power alarm interrupt could happen. low power interrupt pending bit is reg [04h.bit5]. the battery voltage producing low power alarm can be set by the following register. r/w 0 3:2 lbnmi voltage setting one-bat li-ion 00 0.85v 3.0v 01 0.90v 3.1v 10 0.95v 3.3v 11 1.00v 3.5v when battery voltage is lo wer than the default 0.85v (single battery mode) or 3.0v (li-ion battery mode ), the system will send out low power alarm interrupt pending flag. used together with lbnmi_ enable. r/w 00 1:0 reserved r/w 10 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 96 16.7.5 lradc1 (lradc1 data & frequency register, page0_08dh) display lradc1 output data and set adc frequency. bits description access reset 7 the all adcs frequency source select: the all a/d converter?s working frequency is default as 128hz. user can put the working frequency down to 64hz by setting this bit 0 to consume little power. 0: 64hz 1: 128hz r/w 1 6 lradc1/3/4/5 enable. 1: enable 0: disable. r/w 0 5:0 wire-control a/d converter lradc1?s data output. lradc1 input voltage range is from 0 to avcc. r x note: only lradc1 can send interrupt. 16.7.6 lradc2 (lradc2 input detect data register, page0_08eh) the lradc2 data register display lradc2 output data. bits description access reset 7 external dc5v supply presence 1: external 5v supply is present; 0: external 5v supply is not present; r x 6:0 7bit lradc2 for bat temperature. th e input voltage range is 0.7-2.2v. 1lsb= (2.2-0.7)v/27=11.72mv. r x free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 97 16.7.7 batadc (battery voltage detect data register, page0_08fh) the batadc data register displays battery a/d output data. bits description access reset 7 battery a/d and lradc2 (temperature sensor) enable. 1: enable 0: disable. (enable as soon as power up beca use data can only be updated out after waiting for 8ms after enabling. it is not good to the low voltage detection of first power-up) r/w 1 6:0 battery 7bit voltage adc, to detect battery voltage. input voltage range is: 1aaa: 0.7-2.2v li-ion: 1.4-4.4v r x the following register can only be accessed by mcu only when reg [a6h.bit1:0] is set to 01. the registes used when the page0 is sw itched to page1 are as following: 16.7.8 vccout control (vccout control register, page1_088h) move the registers of sd card and avcc registers of audio to pmu. moreover, fm_vccout control is also in this register, shown as the following. bits description access reset 7:6 avcc ldo margin tuning, voltage drops from vcc 00 0.15v 01 0.20v 10 0.25v 11 0.30v r/w 00 5 sd_vccout pmos1 ctrl, loading capacity: 135ma: 0: disable sd card vccout output, shut down pmos1 power switch. 1: enable sd card vccout output, open pmos1 power switch. the pmos1 driver current is 80ma when sdvcc is 5% than vcc. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 98 4 sd_vccout pmos2 ctrl, loading capacity: 100ma: 0: disable sd card vccout output, shut down pmos2 power switch. 1: enable sd card vccout output, open pmos2 power switch. the pmos1 driver current is 40ma when sdvcc is 5% than vcc. r/w 0 3 fm_vccout is used for fm power supply. 0: fm_vccout pin floating, no power out 1: fm_vccout=2.89v, fm_vccout is a ldo. if there is a capacitance at fm _vccout, you should wait a moment after set this bit 1. r/w 0 2 gpio as a multi pin, it can use as fm_vccout for fm power supply. 0: gpioe0 1: fm_vccout r/w 0 1 avdd ldo enable control: 0: avdd ldo disable 1: avdd ldo enable (pay attention to power-up time sequency) r/w 1 0 reserved r x 16.7.9 lradc3 (lradc3 data register, page1_089h) lradc3 data register disp lays lradc3 output data. bits description access reset 7 reserved r/w 0 6 lradc3 control: 0: gpio_f5 is used as gpio_f5 1: gpio_f5 is used as lradc3 r/w 0 5:0 lradc3 data output. lradc3 input voltage range is from 0 to avcc. r x 16.7.10 lradc4 (lradc4 data register, page1_08ah) lradc4 data register disp lays lradc4 output data. free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 99 bits description access reset 7 reserved r/w 0 6 lradc4 control: 0: gpio_f6 is used as gpio_f6 1: gpio_f6 is used as lradc4 r/w 0 5:0 lradc4 data output lradc4 input voltage range is from 0 to avcc. r x 16.7.11 lradc5 (lradc5 data register, page1_08bh) bits description access reset 7 chg_power detection enable: 0: do not carry out chg_power 1: carry out chg_power, chg_power is forced to change 0, supplied by battery, shall be updated afer a certain time. r/w 1 6 lradc5 control: 0: gpio_f7 is used as gpio_f7 1: gpio_f7 is used as lradc5 r/w 0 5:0 lradc5?s data output lradc5 input voltage range is from 0 to avcc. r x 16.7.12 chg control (charger control register, page1_08ch) the charge control register controls the batt ery charge features, including charger circuit activation, charger current configuration. bits description access reset free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 100 7 charging power detection and cabl e plug-in/out detection flag bit chg_power status: 1: charge power, detect cable plug-in. when dc5v?s voltage> bat+0.14v and >3.6v, and debounce time exceeds a certain value, the bit is 1. 0: no charge power, detect cable plug-out. when dc5v voltage< bat+0.07v or <3.5v, and debounce time exceeds certain vakue, the bit is 1. r x 6 the debounce time of chg_power: 0: chg_power?s rising debounce time is ms, chg_power droping debounce time is ms. 1: chg_power?s rising debounce time us, chg_power droping debounce time is us. r/w 0 5 chg_en, enable charge circuit 1: enable charge circuit, no delay, has current immediately. 0: disable charge circuit. charge circuit will not work and consume little power. note: must enable usbvdd before using charger. r/w 0 4 trickle charging mask bit 0: disable trickle charge. whether battery voltage is below or up 3.0v, the charging current will be the value set by ioreg [page2_8ch.bit3:0]. 1: enable trickle charge. when battery voltage is below 3.0v, the charging current will be 1/10 of the value set by ioreg [page2_8ch.bit3:0]. r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 101 3:0 chg_current magnitude of the battery charge current, the current represented by each bits is as follows: 0000 25ma 0001 25ma 0010 50ma 0011 100ma 0100 150ma 0101 200ma 0110 250ma 0111 300ma 1000 350ma 1001 400ma 1010 450ma 1011 500ma others reserved the charging current is adjusted by using the calibration data of usb 6.2k resistor. r/w 0101 16.7.13 chgdet (charge detect register, page1_08dh) the chg status detect register detects magnitude of current charging current charging phase and charging current status. bits description access reset 7 over temperature display when charging: when the detected temperature of charging pipe exceeds the set value, the bit is 1. user can judge whether to decrease charging current or disable charging circuit according to the bit. r x 6 reserved r x free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 102 5:4 charging phase status: 0 0: reserved 0 1: pre-charging 1 0: constant-current-charging 1 1: constant-voltage-charging the two bits will be available only when bit 7 of this register is set. otherwise they will be always read as 00. there are 3 phases through all the charging process: pre-c, cc and cv. the 2bits show which phase the charging at. r xx 3:1 charge current detect 000....0~25%*ichg, ichg is set by ioreg [page2_8ch.bit3:0], indicationg the current charging current is within the 30% of the set value. 001....25%~50%ichg 010....50%~75%ichg 011....75%~87%ichg 100....above 87%ichg others: reserved user can check the current charging current via the 3bits. r x 0 chg_status charging status. 0: not charging, 1: charging. 0: when the charging current is up to 1/10 of set by ioreg [page2_8ch.bit3:0] and last for 1 second, this bit will be from low to high. 1: when the charging current is down to 7.5% of set by ioreg [page2_8ch.bit3:0], this bit will be from high to low as soon as possible. r x 16.7.14 chgasst (charger assistant register, page1_08eh) the charger assistant register supplies assist ant functions to the li-ion battery charge features, such as charger temperature, terminal voltage and so on. bits description access reset 7 from vbat to dc5v diode enable bit 0: disable, default. 1: enable r/w 0 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 103 6 reserved r/w 1 5:4 charge temperature protection control, set protection temperature. when the temperature of the charging circuit>the setting value, send over temperature flag, see charge detect register 00 100 101/116 01 120 111/127 10 135 123/139 11 150 135/153 r/w 11 3:0 to adjust charger limit voltage, the minimum step is 0.1v. 0000 4.05v 0001 4.06v ?? 1110 4.19v 1111 4.20v the above data are the values when the charging current is not less than 10ma, and except for 4.2v which does not have offset, other levels will be relatively low, about 4~6mv. r/w 1111 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 104 17 electrical characteristics 17.1 absolute maximum ratings parameter symbol min max unit ambient temperature tamb -10 +70 storage temperature tstg -55 +150 dc5v -0.3 6.0 v bat -0.3 4.5 v vcc/avcc/pavcc/uvcc/ vccout/lxvcc -0.3 3.6 v vdd/avdd/rtcvdd -0.3 2.2 v supply voltage io_vdd/lxvdd -0.3 4.5 v input voltage +3.3v io -0.3 3.6 v note: 1) even if one of the above parameters exceeds the absolute maximum ratings momentarily, the quality of the product may be degraded. the absolute maximum ratings, therefore, specify the value exceed ing, which the product may be physically damaged. use the product well within these ratings. 2) all voltage values are with respect to gnd 3) +3.3v io/+1.8v io are defined in the pin list. 17.2 recommended power supply vcc = 3.1v tamb = -10 c to 70 c supply voltage min typ max unit bat (li) 3.4 3.8 4.5 v free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 105 bat 1*aaa 0.9 1.2 1.8 v rtcvdd(li) 1.2 1.5 2.0 v rtcvdd 1*aaa 0.9 1.2 2.0 v dc5v 3.9 5 5.5 v vcc/uvcc/avcc/pavcc 2.8 3.1 3.4 v vdd/avdd 1.5 1.7 2.0 v note: according to different application, the vdd voltage can config differently. for optimum cpu perfomance, the vdd should be higher th an 1.6v; for reduced the power consumption, the vdd can supply with 1.6v. 17.3 capacitance parameter symbol condition min. max. unit input capacitance c i 15 pf i/o capacitance c io f c = 1 mhz unmeasured pins returned to 0 v 15 pf note: t o = 25 , vcc = 0 v. 17.4 dc characteristics vcc = 3.1v tamb =-10 c to 70 c parameter symbol min. typ. max. unit low-level input voltage v il 0.8 v high-level input voltage v ih 2.0 v low-level output voltage v ol 0.4 v high-level output voltage v oh 2.4 v 17.5 ac characteristics t o = -10 to +70 free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 106 17.5.1 ac test input waveform 17.5.2 ac test output measuring points 17.5.3 reset parameter parameter symbol condition min. max. unit reset input low-level width t wrsl reset# pin 50 us 17.5.4 initialization parameter parameter symbol condition min. max. unit vcc 0v 0.6vcc 0.4vcc test points 0.4vcc 0.6vcc all input pins free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 107 data sampling time (from reset# ) t ss 61.04 us output delay time (from reset# ) t od 61.04 us 17.5.5 gpio interface parameter parameter symbol condition min. max. unit input level width t gpin 11/f mcuclk s gpio output rise time t gprise 5 50 ns gpio output fall time t gpfall 5 50 ns output level width t gpout normal operation 11/f mcuclk s notes 1. f mcuclk is the frequency that mcu is running upon. input level width free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 108 output rise/fall time output level width 17.5.6 ordinary rom parameter parameter symbol condition min. max. unit data access time (from address) note t acc hosc=24mhz 90 ns data access time (from cex# ) note t ce hosc=24mhz 90 ns data input setup time t ds hosc=24mhz 40 ns data input hold time t dh hosc=24mhz 15 ns free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 109 ordinary rom 17.5.7 external system bus parameter parameter symbol condition min. max. unit address setup time (to command signal) note 1, 2 t xas memory read 10 ns free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 110 t xas memory write 10 ns address hold time (from command signal) note 1, 2 t xah 5 ns data output setup time (to command signal) note 1 t wxds 20 ns data output hold time (from command signal) note 1 t wxdh 10 ns data input setup time (to command signal) note 1 t rxds 20 ns data input hold time (from command signal) note 1 t rxdh 10 ns notes: 1. mrd#, mwr# are called the comma nd signals for the external system bus interface. 2. t (ns) = 1/ f mcuclk 17.5.8 bus operation free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 111 17.5.9 headphone driver characteristics (t o =-10 - +70 , vd d = 1.6 v, vcc = 3.0 v, sample rate=32khz, volume level=0x1f) characteristics min typ max unit dynamic range ?60 dbfs input -87 db total harmonic distortion + noise -81 db frequency response 20-20khz -7.6 0 db output common mode voltage 1.5 v full scale output voltage 1.3 vpp inter channel gain mismatch(1khz) -66 db free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 112 audio2722.at27 color sweep trace line style thick data axi s comment 1 1 blue solid 1 anlr.level a left 1 3 yellow solid 1 anlr.level b left -10 +0 -8 -6 -4 -2 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz frequency response diagram of headphone driver audio2722.at27 color sweep trace line style thick data axi s comment 1 1 blue solid 1 anlr.thd+n ratio left 1 2 yellow solid 1 anlr.thd+n ratio left -100 +0 -80 -60 -40 -20 d b 0 1.4 200m 400m 600m 800m 1 1.2 vpp thd + n amplitude diagram of headphone driver free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 113 18 package drawing 18.1 atj3315 package drawing free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 114 19 ordering information 19.1 recommended soldering conditions soldering conditions for surface-mount devices soldering process soldering conditions peak package?s surface temperature: 235 (lead) or 260 (lead free) reflow time: 30 seconds or less (210 or more)----(lead) or 60 seconds or less (217 or more)---- (lead free) maximum allowable number of reflow processes: 2 infrared ray reflow exposure limit: 1 days at rh=60%, tem=30 (12 hours of pre-baking is required at 125 afterward). terminal temperature: 300 or less partial heating method heat time: 3 seconds or less (for one side of a device) note: the maximum number of days during which th e product can be stored at a temperature of 25 and a relative humidity of 65% or less after dry-pack package is opened. caution: do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). 19.2 precaution against esd for semiconductors when the strong electric field is exposed to a mos device, the destruction of the gate oxide may occur and then it can ultimately degr ade the device operation. measures must be taken to stop the generation of static electricity as many as possible, and it is a must to quickly dissipate the static electricity when it occurs. environmental control must be adequate enough. humidifier should be used when it is dry. recommend to avoid using insulators, which may easily build static electr icity. semiconductor devices must be stored and transported in an anti-static container or a static shielding bag or objects made from conductive material. all test and measurement tools including work bench and floor should be grounded. the operator shall be grounded by using wrist strap. semiconductor devices shall not be touched with bare hands. similar precautions shall be taken for pw boards with semiconductor devices on it. free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 115 19.3 handling of unused input pins for cmos the cause for no connection to cmos device inputs can be the malfunction. if no connection is provided for the input pins, the possible cause is that an internal input level may be generated due to noise, etc., which re sults in malfunction. cmos devices behave differently from bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin shall be connected to vcc or gnd with a resistor, if it is considered to ha ve the possibility of being an output pin. all handling related to the unused pins must be ju dged device by device and follows the related specifications governing the devices. 19.4 status before initialization of mos devices power-on does not necessarily define the initial status of mos device. production process of mos does not define the initial oper ation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin le vels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after the power-on. free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 116 20 appendix 20.1 24.1 acronym and abbreviations ack?acknowledgement adc?analog digital convert atairq?advanced technology attachment interrupt request ctc?clock/timer/counter dac?digital analog convert dma?direct memory address drq?data request dst?destination dst?destination ecc?error correction code em?external memory fifo?first in first out hip?host interface port hosc?high frequency oscillator idm?internal data memory ipm?internal program memory irq?interrupt request ir?infra-red losc?low frequency oscillator mic?microphone nak?negative acknowledgement pll?phase locked loop rtc?real time clock rb?ready/busy sirq?system interrupt request spdif?sony/philips digital interface spi?serial port interface src?source tc?transmit complete uart?universal asynchronous receiver/transmitter free datasheet http://www.datasheet-pdf.com/
ATJ331X datasheet copyright ? actions semiconductor co., ltd. 2010. all rights reserved. version 1.0 page 117 actions semiconductor co., ltd. address: bldg.15-1, no.1, hit rd., tangjia, zhuhai, guangdong, china tel: +86-756-3392353 fax: +86-756-3392251 post code: 519085 http://www.actions-semi.com business email: mp-sales@actions-semi.com technical service email: mp-cs@actions-semi.com free datasheet http://www.datasheet-pdf.com/

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